Intel Cyclone 10 GX User Manual page 3

Contents
2.6. Ethernet............................................................................................................. 86
2.6.1. Gigabit Ethernet (GbE) and GbE with IEEE 1588v2....................................... 87
2.6.2. 10GBASE-R and 10GBASE-R with IEEE 1588v2 Variants............................... 98
2.6.3. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP Core....................... 108
2.6.4. XAUI PHY IP Core...................................................................................121
2.6.5. Acronyms.............................................................................................121
2.7. PCI Express (PIPE)............................................................................................ 122
2.7.1. Transceiver Channel Datapath for PIPE...................................................... 123
2.7.2. Supported PIPE Features......................................................................... 123
2.7.3. How to Connect TX PLLs for PIPE Gen1 and Gen2 Modes............................. 128
2.7.4. How to Implement PCI Express (PIPE) in Cyclone 10 GX Transceivers........... 131
2.7.5. Native PHY IP Parameter Settings for PIPE ............................................... 131
2.7.6. fPLL IP Parameter Core Settings for PIPE................................................... 135
2.7.7. ATX PLL IP Parameter Core Settings for PIPE .............................................137
2.7.8. Native PHY IP Ports for PIPE................................................................... 139
2.7.9. fPLL Ports for PIPE..................................................................................143
2.7.10. ATX PLL Ports for PIPE...........................................................................145
2.7.11. How to Place Channels for PIPE Configurations......................................... 146
2.8. CPRI................................................................................................................149
2.8.1. Transceiver Channel Datapath and Clocking for CPRI...................................149
2.8.2. Supported Features for CPRI ..................................................................151
2.8.3. Word Aligner in Manual Mode for CPRI.......................................................152
2.8.4. How to Implement CPRI in Cyclone 10 GX Transceivers............................... 153
2.8.5. Native PHY IP Parameter Settings for CPRI............................................... 155
2.9. Other Protocols..................................................................................................158
2.9.1. Using the "Basic (Enhanced PCS)" Configuration........................................158
2.9.2. Using the Basic/Custom, Basic/Custom with Rate Match Configurations of
Standard PCS........................................................................................ 166
2.9.3. How to Implement PCS Direct Transceiver Configuration Rule....................... 185
2.10. Simulating the Transceiver Native PHY IP Core..................................................... 186
2.10.1. NativeLink Simulation Flow.................................................................... 187
2.10.2. Scripting IP Simulation..........................................................................192
2.10.3. Custom Simulation Flow........................................................................ 193
2.11. Implementing Protocols in Intel Cyclone 10 GX Transceivers Revision History........... 196
3. PLLs and Clock Networks............................................................................................ 198
3.1. PLLs................................................................................................................. 200
3.1.1. Transmit PLLs Spacing Guidelines when using ATX PLLs and fPLLs................. 200
3.1.2. ATX PLL................................................................................................ 201
3.1.3. fPLL......................................................................................................203
3.1.4. CMU PLL............................................................................................... 206
3.2. Input Reference Clock Sources............................................................................208
3.2.1. Dedicated Reference Clock Pins............................................................... 209
3.2.2. Receiver Input Pins.................................................................................209
3.2.3. PLL Cascading as an Input Reference Clock Source..................................... 210
3.2.4. Reference Clock Network.........................................................................210
3.2.5. Global Clock or Core Clock as an Input Reference Clock............................... 210
3.3. Transmitter Clock Network..................................................................................210
3.3.1. x1 Clock Lines....................................................................................... 211
3.3.2. x6 Clock Lines....................................................................................... 212
3.3.3. xN Clock Lines....................................................................................... 214
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Intel Cyclone 10 GX Transceiver PHY User Guide
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