Intel Cyclone 10 GX User Manual page 298

Deletable Case
Upper Word
If only one word is deleted, data shifting is necessary because the datapath is two
words wide. After two words have been deleted, the FIFO stops writing for one cycle
and a synchronous flag (
There is also an asynchronous status signal
through the FIFO.
Figure 192. IDLE Word Deletion
This figure shows the deletion of IDLE words from the receiver data stream.
rx_parallel_data[79:0]
rx_parallel_data[79:0]
Figure 193. OS Word Deletion
This figure shows the deletion of Ordered set words in the receiver data stream.
Before Deletion
rx_parallel_data[79:0]
FD000000000004AEh
After Deletion
rx_parallel_data[79:0]
FD000000000004AEh
Idle Insertion
Idle insertion occurs in groups of 8 Idles when the
deasserted. Idles can be inserted following Idles or OS. Idles are inserted in groups of
8 bytes. Data shifting is not necessary. There is a synchronous status
rx_enh_fifo_insert
Table 170. Cases Where Two Idle Words are Inserted
In this table X=don't care, S=start, OS=order set, I-DS=idle in data stream, and I-In=idle inserted. In cases 3
and 4, the Idles are inserted between the LW and UW.
Case
1
2
3
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
298
Word
LW
1 UW
LW
2 UW
LW
rx_control[8]
Before Deletion
00000000000004ADh
After Deletion
00000000000004ADh
DDDDDD9CDDDDDD9Ch
000000FBDDDDDD9Ch
signal that is attached to the 8-byte Idles being inserted.
Word
UW
LW
UW
LW
UW
5. Cyclone 10 GX Transceiver PHY Architecture
Previous Current
X OS
X I
X !T
X OS
X OS
) appears on the next block of 8-byte data.
rx_enh_fifo_del
00000000000004AEh 0707070707FD0000h
00000000000004AEh
0707070707FD0000h
00000000000000FBh
AAAAAAAA00000000h
rx_enh_fifo_pempty
Input
I-DS I-DS
X
OS
X
S
UG-20070 | 2018.09.24
Output
X
X
X
X
X OS
, which does not go
000000FB07070707h
AAAAAAAA000000FBh
Idle Deleted
AAAAAAAAAAAAAAAAh
00000000AAAAAAAAh
OS Deleted
flag is
Output
I-In
X I-In
OS I-In
X I-In
I-In S
continued...
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X
X
!T
X