Intel Cyclone 10 GX User Manual page 202

Phase Frequency Detector (PFD)
The reference clock
feedback clock
inputs to the PFD. The output of the PFD is proportional to the phase difference
between the
output of the N counter to the feedback clock
"Up" signal when the reference clock's falling edge occurs before the feedback clock's
falling edge. Conversely, the PFD generates a "Down" signal when the feedback clock's
falling edge occurs before the reference clock's falling edge.
Charge Pump and Loop Filter
The PFD output is used by the charge pump and loop filter (CP and LF) to generate a
control voltage for the VCO. The charge pump translates the "Up" or "Down" pulses
from the PFD into current pulses. The current pulses are filtered through a low pass
filter into a control voltage that drives the VCO frequency. The charge pump, loop
filter, and VCO settings determine the bandwidth of the ATX PLL.
Lock Detector
The lock detector block indicates when the reference clock and the feedback clock are
phase aligned. The lock detector generates an active high
indicate that the PLL is locked to its input reference clock.
Voltage Controlled Oscillator
The voltage controlled oscillator (VCO) used in the ATX PLL is LC tank based. The
output of charge pump and loop filter serves as an input to the VCO. The output
frequency of the VCO depends on the input control voltage. The output frequency is
adjusted based on the output voltage of the charge pump and loop filter.
L Counter
The L counter divides the differential clocks generated by the ATX PLL. The L counter
is not in the feedback path of the PLL.
M Counter
The M counter's output is the same frequency as the N counter's output. The VCO
frequency is governed by the equation:
VCO freq = 2 * M * input reference clock/N
An additional divider divides the high speed serial clock output of the VCO by 2 before
it reaches the M counter.
The M counter supports division factors in a continuous range from 8 to 127 in integer
frequency synthesis mode.
Multiple Reconfiguration Profiles
Under the ATX PLL IP Parameter Editor Dynamic Reconfiguration tab, in the
Configuration Profiles section, multiple reconfiguration profiles can be enabled. This
allows to create, store, and analyze the parameter settings for multiple configurations
or profiles of the ATX PLL IP.
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
202
signal at the output of the N counter block and the
(refclk)
signal at the output of the M counter block are supplied as
(fbclk)
and inputs. It is used to align the
refclk fbclk
3. PLLs and Clock Networks
UG-20070 | 2018.09.24
refclk
signal. The PFD generates an
(fbclk)
pll_locked
signal at the
signal to
Send Feedback