Intel Cyclone 10 GX User Manual page 27

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Figure 11. Native PHY IP Core Ports and Functional Blocks
Transmit Parallel Data
Receive Parallel Data
Reset Signals
Reconfiguration Interface
Transmit and Receive Clocks
Figure 12. Native PHY IP Core Parameter Editor
Note: Although the Quartus Prime software provides legality checks, refer to the High-Speed
Serial Transceiver-Fabric Interface Performance for Intel Cyclone 10 GX Devices
section of theIntel Cyclone 10 GX Device Datasheet for the supported FPGA fabric to
PCS interface widths and frequency.
Related Information
• Configure the PHY IP Core
• Interlaken
• Gigabit Ethernet (GbE) and GbE with IEEE 1588v2
Send Feedback
Enhanced PCS
Standard PCS
PCS-Direct
Reconfiguration
Registers
on page 19
on page 70
Transmit
PMA
Receive
PMA
Nios II
Calibration
on page 87
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
Transmit Serial Data
Receive Serial Data
Calibration Signals
27