Intel Cyclone 10 GX User Manual page 199

3. PLLs and Clock Networks
UG-20070 | 2018.09.24
Figure 118. Cyclone 10 GX PLLs and Clock Networks
Related Information
• Channel Bonding
• Device Transceiver Layout
• Using PLLs and Clock Networks
Information on how to use PLL IP to implement bonded and non-bonded
transceiver designs.
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CH3
CDR
Local CGB
CH2
CDR
Local CGB
CH1
CDR/CMU
Local CGB
CH0
CDR
Local CGB
CH5
CDR
Local CGB
CH4
CDR/CMU
Local CGB
CH3
CDR
Local CGB
CH2
CDR
Local CGB
CH1
CDR/CMU
Local CGB
CH0
CDR
Local CGB
on page 222
on page 8
x1 Clock Lines x6 Clock Lines
on page 231
®
Intel Cyclone
Transceiver
xN Clock Lines
Bank
fPLL
ATX
PLL
Master
CGB
fPLL
ATX
PLL
Master
CGB
Transceiver
Bank
fPLL
ATX
PLL
Master
CGB
fPLL
ATX
PLL
Master
CGB
®
10 GX Transceiver PHY User Guide
199