Intel Cyclone 10 GX User Manual page 392

Assign To
RX serial data pin.
Syntax
set_instance_assignment -name XCVR_C10_RX_EQ_DC_GAIN_TRIM <value>
-to <rx_serial_data pin name>
8.5.1.3. XCVR_C10_RX_ADP_CTLE_ACGAIN_4S
Pin planner or Assignment Editor Name
Receiver High Gain Mode Equalizer AC Gain Control
Description
Controls the AC gain of the continuous time linear equalizer (CTLE) in high gain mode.
The default value is RADP_CTLE_ACGAIN_4S_1.
Table 219. Available Options
RADP_CTLE_ACGAIN_4S_<0 to 28>
Assign To
RX serial data pin.
Syntax
set_instance_assignment -name XCVR_C10_RX_ADP_CTLE_ACGAIN_4S
<value> -to <rx_serial_data pin name>
8.5.1.4. XCVR_C10_RX_ADP_CTLE_EQZ_1S_SEL
Pin planner or Assignment Editor Name
Receiver High Data Rate Mode Equalizer AC Gain Control
Description
Controls the AC gain of the continuous time linear equalizer (CTLE) in high data rate
mode.
In high data rate mode, there is only one CTLE stage and 16 possible AC gain settings.
Higher gain setting results in larger AC gain. The default value is set to
RADP_CTLE_EQZ_1S_SEL_3 i.e. CTLE AC Gain Setting 3. This QSF assignment only
takes effect when one stage CTLE is enabled. If configured in four stage mode, it has
no effect on CTLE gain value.
Table 220. Available Options
RADP_CTLE_EQZ_1S_SEL_<0 to 15>
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
392
Value
Value
8. Analog Parameter Settings
UG-20070 | 2018.09.24
Description
CTLE AC gain setting <0 to 28>
Description
CTLE AC Gain Setting < 0 to 15>
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