Intel Cyclone 10 GX User Manual page 266

Signal Name
tx_analogreset[<n>-1:
0]
tx_ready[<n>-1:0]
rx_digitalreset[<n>
-1:0]
rx_analogreset
[<n>-1:0]
rx_ready[<n>-1:0]
pll_powerdown[<p>-1:0
]
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
266
Direction Clock Domain
Output Synchronous to the
Transceiver PHY Reset
Controller input clock.
Output Synchronous to the
Transceiver PHY Reset
Controller input clock.
Output Synchronous to the
Transceiver PHY Reset
Controller input clock.
Output Synchronous to the
Transceiver PHY Reset
Controller input clock.
Output Synchronous to the
Transceiver PHY Reset
Controller input clock.
Output Synchronous to the
Transceiver PHY Reset
Controller input clock.
4. Resetting Transceiver Channels
Description
Analog reset for TX channels. The width of this signal
depends on the number of TX channels. This signal is
asserted when is asserted.
reset
This signal follows
pll_powerdown
deasserted after
pll_locked
Status signal to indicate when the TX reset sequence is
complete. This signal is deasserted while the TX reset
is active. It is asserted a few clock cycles after the
deassertion of
tx_digitalreset
implementations may require you to monitor this signal
prior to sending data. The width of this signal depends
on the number of TX channels.
Digital reset for RX. The width of this signal depends
on the number of channels. This signal is asserted
when any of the following conditions is true:
•
is asserted
reset
•
is asserted
rx_analogreset
•
is asserted
rx_cal_busy
•
is deasserted and
rx_is_lockedtodata
is deasserted
rx_manual
When all of these conditions are false, the reset
counter begins its countdown for deassertion of
.
rx_digitalreset
Analog reset for RX. When asserted, resets the RX CDR
and the RX PMA blocks of the transceiver PHY. This
signal is asserted when any of the following conditions
is true:
•
is asserted
reset
•
is asserted
rx_cal_busy
The width of this signal depends on the number of
channels.
Status signal to indicate when the RX reset sequence is
complete. This signal is deasserted while the RX reset
is active. It is asserted a few clock cycles after the
deassertion of
rx_digitalreset
implementations may require you to monitor this signal
prior to sending data. The width of this signal depends
on the number of RX channels.
Asserted to power down a transceiver PLL circuit. When
asserted, the selected TX PLL is reset.
UG-20070 | 2018.09.24
, which is
goes high.
. Some protocol
. Some protocol
Send Feedback