intel Stratix 10 Manuals

Manuals and User Guides for intel Stratix 10. We have 4 intel Stratix 10 manuals available for free PDF download: User Manual, Configuration User Manual

Intel Stratix 10 User Manual (228 pages)

E-Tile Transceiver PHY

Brand: Intel | Category: Transceiver | Size: 12.97 MB

Table of Contents
2
1 Intel ® Stratix ® 10 E-Tile Transceiver PHY Overview

7
2 Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices

24
3 Intel Stratix 10 E-Tile Transceiver PHY Architecture

56
4 Clock Network

86
5 PMA Calibration

98
- PMA Calibration Revision History
  99
6 Resetting Transceiver Channels

100
- When Is Reset Required
  100
- How Do I Reset
  100
  - Resetting the Intel Stratix 10 E-Tile Transceiver
    101
  - Selecting the Reset Controller's Clock Source
    102
- Reset Block Architecture
  102
- PMA Analog Reset
  104
- High Level Specification
  105
  - Automatic Reset Mode
    105
  - Manual Reset Mode
    107
  - Reset Controller Bypass
    112
- Intel Quartus Prime Instantiated Transceiver Reset Sequencer
  114
- Block Diagrams
  115
- Interfaces
  117
  - Reset Parameters in the Native PHY GUI
    117
  - HDL Ports/Interfaces
    117
- Resetting Transceiver Channels Revision History
  118
7 Dynamic Reconfiguration

119
8 Dynamic Reconfiguration Examples

140
9 Register Map

165
- PMA Register Map
  165
  - PMA Capability Registers
    165
  - PMA Control and Status Registers
    166
  - PMA AVMM Registers
    167
- PMA Attribute Codes
  170
- PMA Registers 0X200 to 0X203 Usage
  184
- Supported Data Rate Ratios for PMA Attribute Codes 0X0005 and 0X0006
  187
- RS-FEC Registers
  190
  - Rsfec_Top_Clk_Cfg
    193
  - Rsfec_Top_Tx_Cfg
    194
  - Rsfec_Top_Rx_Cfg
    195
  - Tx_Aib_Dsk_Conf
    196
  - Rsfec_Core_Cfg
    196
  - Rsfec_Lane_Cfg
    197
  - Tx_Aib_Dsk_Status
    197
  - Rsfec_Debug_Cfg
    198
  - Rsfec_Lane_Tx_Stat
    199
  - Rsfec_Lane_Tx_Hold
    199
  - Rsfec_Lane_Tx_Inten
    200
  - Rsfec_Lane_Rx_Stat
    200
  - Rsfec_Lane_Rx_Hold
    201
  - Rsfec_Lane_Rx_Inten
    202
  - Rsfec_Lanes_Rx_Stat
    203
  - Rsfec_Lanes_Rx_Hold
    203
  - Rsfec_Lanes_Rx_Inten
    204
  - Rsfec_Ln_Mapping_Rx
    204
  - Rsfec_Ln_Skew_Rx
    205
  - Rsfec_Cw_Pos_Rx
    205
  - Rsfec_Core_Ecc_Hold
    205
  - Rsfec_Err_Inj_Tx
    206
  - Rsfec_Err_Val_Tx
    206
  - Rsfec_Corr_Cw_Cnt (Low)
    207
  - Rsfec_Corr_Cw_Cnt (High)
    207
  - Rsfec_Uncorr_Cw_Cnt (Low)
    208
  - Rsfec_Uncorr_Cw_Cnt (High)
    208
  - Rsfec_Corr_Syms_Cnt (Low)
    208
  - Rsfec_Corr_Syms_Cnt (High)
    209
  - Rsfec_Corr_0S_Cnt (Low)
    209
  - Rsfec_Corr_0S_Cnt (High)
    210
  - Rsfec_Corr_1S_Cnt (Low)
    210
  - Rsfec_Corr_1S_Cnt (High)
    210
- Register Map Revision History
  211
E-Tile Channel Placement Tool

212
- E-Tile Channel Placement Tool Revision History
  212
PMA Direct PAM4 30 Gbps to 57.8 Gbps Implementation

214

intel Stratix 10 Configuration User Manual (113 pages)

GX FPGA Development Kit

Brand: intel | Category: Microcontrollers | Size: 2.22 MB

Intel Stratix 10 User Manual (56 pages)

Device Security

Brand: Intel | Category: Control Unit | Size: 1.08 MB

Intel Stratix 10 User Manual (45 pages)

Device Security

Brand: Intel | Category: Computer Hardware | Size: 0.96 MB

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More intel Manuals

intel Stratix 10 Manuals

Intel Stratix 10 User Manual (228 pages)

Table of Contents

1 Intel ® Stratix ® 10 E-Tile Transceiver PHY Overview

2 Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices

3 Intel Stratix 10 E-Tile Transceiver PHY Architecture

4 Clock Network

5 PMA Calibration

6 Resetting Transceiver Channels

7 Dynamic Reconfiguration

8 Dynamic Reconfiguration Examples

9 Register Map

E-Tile Channel Placement Tool

PMA Direct PAM4 30 Gbps to 57.8 Gbps Implementation

intel Stratix 10 Configuration User Manual (113 pages)

Table of Contents

1 Intel ® Stratix ® 10 Configuration Overview

2 Intel Stratix 10 Configuration Details

3 Intel Stratix 10 Configuration Schemes

4 Stratix 10 Configuration Features

5 Remote System Upgrade

6 Intel Stratix 10 Debugging Guide

7 Intel Stratix 10 Configuration User Guide Archives

8 Document Revision History for the Intel Stratix 10 Configuration User Guide

Intel Stratix 10 User Manual (56 pages)

Table of Contents

1 Intel ® Stratix ® 10 Device Security Overview

2 Design Authentication

3 Using the Authentication Feature

4 Co-Signing Device Firmware Overview

5 HPS Debug Using a Certificate

6 Signing Command Detailed Description

7 Encryption and Decryption Overview

8 Encryption Command Detailed Description

9 Using Efuses

10 Document Revision History for Intel Stratix 10 Device Security User Guide

Intel Stratix 10 User Manual (45 pages)

Table of Contents

1 Intel ® Stratix ® 10 Device Security Overview

2 Design Authentication

3 Using the Authentication Feature

4 Co-Signing Device Firmware Overview

5 Signing Command Detailed Description

6 Encryption and Decryption Overview

7 Using Efuses

8 Document Revision History for Intel Stratix 10 Device Security User Guide

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