Atx Pll Ports For Pipe - Intel Cyclone 10 GX User Manual

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24

2.7.10. ATX PLL Ports for PIPE

Table 129. ATX PLL Ports for PIPE
This section contains the recommended settings for this protocol. Refer to Using the Cyclone 10 GX Transceiver
Native PHY IP Core for the full range of parameter settings.
Port
Pll_powerdown
Pll_reflck0
tx_serial_clk
pll_locked
pll_pcie_clk
Pll_cal_busy
Mcgb_rst
tx_bonding_clocks[5:0]
pcie_sw[1:0]
pcie_sw_done[1:0]
Related Information
Using the Cyclone 10 GX Transceiver Native PHY IP Core
Send Feedback
Direction Clock Domain
Input Asynchronous Resets the PLL when asserted high. Needs to be connected to
the Transceiver PHY Reset Controller
Input N/A Reference clock input port 0. There are five reference clock
input ports. The number of reference clock ports available
depends on the Number of PLL reference clocks parameter.
Output N/A High speed serial clock output port for GX channels. Represents
the x1 clock network.
For Gen1x1, Gen2x1, connect the output from this port to the
tx_serial_clk input of the native PHY IP.
For Gen1x2, x4 use the
port to connect to the Native PHY.
For Gen2x2, x4 use the
port to connect to the Native PHY.
Output Asynchronous Active high status signal which indicates if PLL is locked.
Output N/A This is the hclk required for PIPE interface.
For Gen1x1,x2,x4 use this port to drive the
the PIPE interface.
For Gen2x1,x2,x4 use this port to drive the
the PIPE interface.
Output Asynchronous Status signal which is asserted high when PLL calibration is in
progress. If this port is not enabled in the Transceiver PHY
Reset Controller, then perform logical OR with this signal and
the
tx_cal_busy
Input Asynchronous Master CGB reset control.
Output N/A Optional 6-bit bus which carries the low speed parallel clock
outputs from the Master CGB. Used for channel bonding, and
represents the x6/xN clock network.
For Gen1x1, this port is disabled.
For Gen1x2,x4 connect the output from this port to the
tx_bonding_clocks[5:0]
For Gen2x1, this port is disabled
For Gen2x2,x4 connect the output from this port to
tx_bonding_clocks[5:0]
Input Asynchronous 2-bit rate switch control input used for PCIe protocol
implementation.
For Gen1, this port is N/A.
For Gen 2x2,x4 connect the
PHY to this port.
Output Asynchronous 2-bit rate switch status output used for PCIe protocol
implementation.
For Gen1, this port is N/A.
For Gen2x2, x4 connect the
ATX PLL to
Description
tx_bonding_clocks[5:0]
tx_bonding_clocks[5:0]
output signal from Native PHY to input the
tx_cal_busy
on the reset controller IP.
input on Native PHY.
input on Native PHY.
pipe_sw[1:0]
pcie_sw_done[1:0]
input of Native PHY .
pipe_sw_done
on page 26
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
output.
pll_powerdown
output
output
on
pipe_hclk_in
on
pipe_hclk_in
output from Native
output from
145