Simulating The Transceiver Native Phy Ip Core - Intel Cyclone 10 GX User Manual

Figure 114. Connection Guidelines for a PCS Direct PHY Design
pll_refclk
8. Simulate your design to verify its functionality.

2.10. Simulating the Transceiver Native PHY IP Core

Use simulation to verify the Native PHY transceiver functionality. The Quartus Prime
software supports register transfer level (RTL) and gate-level simulation in both
ModelSim
your Quartus Prime project files.
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Intel Cyclone 10 GX Transceiver PHY User Guide
186
PLL IP Core
pll_cal_busy
tx_serialclk0
rx_cdr_refclk
tx_clkout
Data
Generator
tx_parallel_data
rx_clkout
Data
Verifier rx_parallel_data
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- Intel FPGA Edition and third-party simulators. You run simulations using
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
clk
reset
Reset Controller
pll_sel
pll_locked
Cyclone 10 GX Transceiver Native PHY
UG-20070 | 2018.09.24
tx_ready
rx_ready
tx_serial_data
rx_serial_data
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