Intel Cyclone 10 GX User Manual page 44

Parameter
Enable rx_std_wa_a1a2size port
Enable
rx_std_bitslipboundarysel port
Enable rx_bitslip port
Table 30. Bit Reversal and Polarity Inversion
Parameter
Enable TX bit reversal
Enable TX byte reversal
Enable TX polarity
inversion
Enable tx_polinv port
Enable RX bit reversal
Enable rx_std_bitrev_ena
port
Enable RX byte reversal
Enable
rx_std_byterev_ena port
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Intel Cyclone 10 GX Transceiver PHY User Guide
44
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
Range
On / Off
Enables the optional
port.
On / Off
Enables the optional
output port.
On / Off
Enables the
the Standard PCS and Enhanced PCS.
Range
On / Off When you turn on this option, the 8B/10B Encoder reverses TX
parallel data before transmitting it to the PMA for serialization.
The transmitted TX data bit order is reversed. The normal order
is LSB to MSB. The reverse order is MSB to LSB. During the
operation of the circuit, this setting can be changed through
dynamic reconfiguration.
On / Off When you turn on this option, the 8B/10B Encoder reverses the
byte order before transmitting data. This function allows you to
reverse the order of bytes that were erroneously swapped. The
PCS can swap the ordering of either one of the 8- or 10-bit
words, when the PCS/PMA interface width is 16 or 20 bits. This
option is not valid under certain Transceiver configuration
rules.
On / Off
When you turn on this option, the
polarity inversion of TX parallel data to the PMA. When you turn
on this parameter, you also need to turn on the Enable
tx_polinv port.
On / Off
When you turn on this option, the
is enabled. You can use this control port to swap the positive and
negative signals of a serial differential link, if they were
erroneously swapped during board layout.
On / Off When you turn on this option, the word aligner reverses RX
parallel data. The received RX data bit order is reversed. The
normal order is LSB to MSB. The reverse order is MSB to LSB.
This setting can be changed through dynamic reconfiguration.
When you enable Enable RX bit reversal, you must also enable
Enable rx_std_bitrev_ena port.
On / Off When you turn on this option and assert the
rx_std_bitrev_ena
reversed. The normal order is LSB to MSB. The reverse order is
MSB to LSB.
On / Off When you turn on this option, the word aligner reverses the byte
order, before storing the data in the RX FIFO. This function allows
you to reverse the order of bytes that are erroneously swapped.
The PCS can swap the ordering of either one of the 8- or 10-bit
words, when the PCS / PMA interface width is 16 or 20 bits. This
option is not valid under certain Transceiver configuration
rules.
When you enable Enable RX byte reversal, you must also
select the Enable rx_std_byterev_ena port.
On / Off When you turn on this option and assert the
rx_std_byterev_ena
individual 8- or 10-bit words received from the PMA is swapped.
UG-20070 | 2018.09.24
Description
rx_std_wa_a1a2size
rx_std_bitslipboundarysel
port. This port is shared between
rx_bitslip
Description
tx_std_polinv
tx_polinv
control port, the RX data order is
input control port, the order of the
control input
status
port controls
input control port
continued...
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