Intel Cyclone 10 GX User Manual page 310

resulting 20-bit data is [[10..20],[0..9]]. For example, if the 20-bit data is
11001100001000011111, the byte reversal feature changes the data to
10000111111100110000.
5.3.2.2. RX Polarity Inversion Feature
The RX polarity inversion feature inverts each bit of the data received from the PMA. If
the data received is a 10-bit data. Bit[0] content is inverted to its complement,
~bit[0], bit[1] is inverted to its complement, ~bit[1], bit[2] is inverted to its
complement, ~bit[2], and so on. For example, if the 10-bit data is 1111100000, the
polarity inversion feature inverts it to 0000011111.
5.3.2.3. Rate Match FIFO
The rate match FIFO compensates for the frequency differences between the local
clock and the recovered clock up to ± 300 ppm by inserting and deleting skip/idle
characters in the data stream. The rate match FIFO has several different protocol
specific modes of operation. All of the protocol specific modes depend upon the
following parameters:
• Rate match deletion—occurs when the distance between the write and read
pointers exceeds a certain value due to write clock having a higher frequency than
the read clock.
• Rate match insertion—occurs when the distance between the write and the read
pointers becomes less than a certain value due to the read clock having a higher
frequency than the write clock.
• Rate match full—occurs when the write pointer wraps around and catches up to
the slower-advancing read pointer.
• Rate match empty—occurs when the read pointer catches up to the slower-
advancing write pointer.
Rate match FIFO operates in six modes:
• Basic single width
• Basic double width
• GigE
• PIPE
• PIPE 0 ppm
• PCIe
Related Information
• How to Implement GbE, GbE with IEEE 1588v2 in Intel Cyclone 10 GX
Transceivers
For more information about implementing rate match FIFO in GigE mode.
• PCI Express (PIPE)
For more information about implementing rate match FIFO in PCIe mode.
• Using the Basic/Custom, Basic/Custom with Rate Match Configurations of Standard
PCS on page 166
• How to Implement the Basic Rate Match Protocol Using the Cyclone 10 GX
Transceiver Native PHY IP Core
For more information about implementing rate match FIFO for each mode.
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Intel Cyclone 10 GX Transceiver PHY User Guide
310
on page 93
on page 122
on page 166
5. Cyclone 10 GX Transceiver PHY Architecture
UG-20070 | 2018.09.24
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