Intel Cyclone 10 GX User Manual page 228

To support PLL feedback compensation bonding and PLL cascading, the following
connections are present:
1. The C counter output of the fPLL drives the feedback and cascading clock
network.
2. The feedback and cascading clock network drives the feedback clock input of
all PLLs.
3. The feedback and cascading clock network drives the reference clock input of
all PLLs.
4. The master CGB's parallel clock output drives the feedback and cascading
clock network.
For PLL cascading, connections (1) and (3) are used to connect the output of one PLL
to the reference clock input of another PLL.
The transceivers in Cyclone 10 GX devices support fPLL to fPLL. Only a
maximum of two PLLs are allowed in the cascading chain.
Note: When the fPLL is used as a cascaded fPLL (downstream fPLL), a user recalibration on
the fPLL is required. Refer to "User Recalibration" section in "Calibration" chapter for
more information.
For PLL feedback compensation bonding, connections (2) and (4) are used to connect
the master CGB's parallel clock output to the PLL feedback clock input port.
PLL feedback compensation bonding can be used instead of xN bonding. The primary
difference between PLL feedback compensation and xN bonding configurations, is for
PLL feedback compensation, the bonded interface is broken down into smaller groups
of 6 bonded channels within a transceiver bank. A PLL within each transceiver bank
(ATX PLL or fPLL) is used as a transmit PLL. All the transmit PLLs share the same input
reference clock.
In xN bonding configurations, one PLL is used for each bonded group. In PLL feedback
compensation bonding, one PLL is used for each transceiver bank that the bonded
group spans. There are no data rate limitations in PLL feedback compensation
bonding, other than the natural data rate limitations of the transceiver channel and
the PLL.
For feedback compensation bonding, the low-speed parallel clock must be the same
frequency as the reference clock for the PLL.
fPLL Driving the Core
The fPLL can be used to drive the FPGA fabric. To ensure phase alignment between the
input reference clock and the fPLL output clock, the fPLL needs to be configured in
integer mode. Refer to the following figures when doing dynamic reconfiguration.
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Intel Cyclone 10 GX Transceiver PHY User Guide
228
3. PLLs and Clock Networks
UG-20070 | 2018.09.24
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