Intel Cyclone 10 GX User Manual page 230

Figure 137. Integer Mode phase aligned and external feedback
Related Information
• User Recalibration
• Implementing PLL Cascading
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
230
fPLL 1
fpll_t_iqtxrxclk
C
pm_iqtxrxclk_top[5:0]
refclk
pm_iqtxrxclk_top[3:0]
fbclk
PMA_RX_CLK
PMA_TX_CLK
RX pin (1)
fbclk
refclk
PMA_RX_CLK
PMA_TX_CLK
RX pin (1)
PMA_RX_CLK
PMA_TX_CLK
RX pin (1)
fbclk
refclk
PMA_RX_CLK
PMA_TX_CLK
RX pin (1)
PMA_RX_CLK
PMA_TX_CLK
RX pin (1)
fbclk
refclk
PMA_RX_CLK
PMA_TX_CLK
RX pin (1)
ATX PLL 1
lc_t_iqtxrxclk
M
pm_iqtxrxclk_top[5:0]
refclk
pm_iqtxrxclk_top[3:0]
fbclk
Master
CGB 1
Note: (1) RX pin used as reference clock
on page 383
on page 240
6
4
Ch5
ch5_iqtxrxclk_2
pm_iqtxrxclk_top[5:0]
4
pm_iqtxrxclk_top[3:0]
6
ch5_iqtxrxclk_5
Ch4
ch4_iqtxrxclk_4
pm_iqtxrxclk_top[5:0]
4
pm_iqtxrxclk_top[3:0]
6
ch4_iqtxrxclk_4
Ch3
ch3_iqtxrxclk_0
pm_iqtxrxclk_top[5:0]
4
pm_iqtxrxclk_top[3:0]
6
ch3_iqtxrxclk_5
6
4
3. PLLs and Clock Networks
UG-20070 | 2018.09.24
pm_iqtxrx_t[5:0]
0 1 2 3 4 5
Send Feedback