Intel Cyclone 10 GX User Manual page 181

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Figure 112. Signals and Ports of Native PHY IP for Basic, Basic with Rate Match
Configurations
tx_parallel_data[7:0]
rx_parallel_data[7:0]
5. Instantiate and configure your PLL.
6. Create a transceiver reset controller.
7. Connect the Native PHY IP to the PLL IP and the reset controller. Use the
information in
Figure 113. Connection Guidelines for a Basic/Custom Design
8. Simulate your design to verify its functionality.
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Cyclone 10 Transceiver Native PHY
reconfig_reset
Reconfiguration
reconfig_clk
Registers
reconfig_avmm
TX Standard PCS
tx_digital_reset
tx_datak tx_datak
tx_parallel_data[7:0]
tx_coreclkin
tx_clkout tx_clkout
unused_tx_parallel_data[118:0]
tx_analog_reset
rx_analog_reset
RX Standard PCS
rx_digital_reset
rx_datak
rx_datak
rx_parallel_data[7:0]
rx_clkout rx_clkout
rx_coreclkin
rx_errdetect rx_errdetect
rx_disperr
rx_disperr
rx_runningdisp
rx_runningdisp
rx_patterndetect
rx_patterndetect
rx_syncstatus
rx_syncstatus
rx_rmfifostatus (1) rx_rmfifostatus (1)
unused_rx_parallel_data[113:0]
Note:
1. Only applies when using the Basic with Rate Match transceiver configuration rule.
Transceiver Native PHY Ports for the Protocol
Pattern
reset
Generator
pll_ref_clk
pll_locked
PLL IP
pll_powerdown
Reset
Controller
rx_ready
tx_ready
clk
reset
Pattern
reset
Checker
tx_serial_clk
Nios Hard
Calibration IP
TX PMA
10
Serializer
Central/Local
Clock Divider
RX PMA
10
Deserializer CDR
tx_parallel_data
tx_datak
tx_clkout
tx_digital_reset
tx_analog_reset
rx_digital_reset
Cyclone 10
rx_analog_reset
Transceiver
rx_is_lockedtoref Native
PHY
rx_is_lockedtodata
rx_parallel_data
rx_datak
rx_clkout
® ®
Intel Cyclone
tx_cal_busy
rx_cal_busy
tx_serial_data
tx_serial_clk0 (from TX PLL)
rx_serial_data
rx_cdr_refclk0
rx_is_lockedtodata
rx_is_lockedtoref
to connect the ports.
tx_serial_data
rx_serial_data
rx_cdr_refclk
reconfig_clk
reconfig_reset
reconfig_write
reconfig_read
For
reconfig_address
Reconfiguration
reconfig_writedata
reconfig_readdata
reconfig_waitrequest
cal_busy
10 GX Transceiver PHY User Guide
181