Intel Cyclone 10 GX User Manual page 77

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Figure 23. TX FIFO Pre-fill (6-lane Interface)
tx_enh_data_valid
tx_enh_fifo_pfull
tx_enh_fifo_empty
tx_enh_fifo_pempty
tx_enh_frame_burst_en
After the TX FIFO pre-fill stage completes, the transmit lanes synchronize and the MAC
layer begins to send valid data to the transceiver's TX FIFO. You must never allow the
TX FIFO to overflow or underflow. If it does, you must reset the transceiver and repeat
the TX FIFO pre-fill stage.
For a single lane Interlaken implementation, TX FIFO soft bonding is not required. You
can begin sending an Interlaken word to the TX FIFO after
deasserts.
The following figure shows the MAC layer sending valid data to the Native PHY after
the pre-fill stage.
generator to read data from the TX FIFO. The TX MAC layer can now control
tx_enh_data_valid
Figure 24. MAC Sending Valid Data (6-lane Interface)
tx_enh_data_valid
tx_enh_fifo_pfull
tx_enh_fifo_empty
tx_enh_fifo_pempty
tx_enh_frame_burst_en
2.5.2.2.2. RX Multi-lane FIFO Deskew State Machine
Add deskew logic at the receiver side to eliminate the lane-to-lane skew created at the
transmitter of the link partner, PCB, medium, and local receiver PMA.
Implement a multi-lane alignment deskew state machine to control the RX FIFO
operation based on available RX FIFO status flags and control signals.
Send Feedback
Deassert tx_digitalreset
tx_digitalreset 3f 00
00 3f
tx_enh_fifo_full 00
00
3f
3f
tx_enh_fifo_cnt 000000
tx_enh_frame 00
00
Deassert burst_en for all Lanes and Fill
TX FIFO Until all Lane FIFOs Are Full
tx_enh_frame_burst_en
and write data to the TX FIFO based on the FIFO status signals.
tx_digitalreset 00
00
tx_enh_fifo_full 3f
3f
00
00
tx_enh_fifo_cnt ffffff
tx_enh_frame 00
3f
After the Pre-fill Stage, Assert burst_en.
The Frame Generator Reads Data from
the TX FIFO for the Next Metaframe
00
1... 2... 3... 4... 5... 6... 7... 8... 9... a... b... c... d... e... ffffff
3f
is asserted, allowing the frame
00
00
3f 00
The User Logic Asserts data_valid
to Send Data to the TX FIFO Based
on the FIFO Status
®
Intel Cyclone
00
3f
3f
00
tx_digitalreset
3f
The TX FIFO
Writes Backpressure
®
10 GX Transceiver PHY User Guide
00
3f
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