Intel Cyclone 10 GX User Manual page 81

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Figure 28. Connection Guidelines for an Interlaken PHY Design
This figure shows and example connection for an Interlake PHY design.
For the blue blocks, Intel provides an IP core. The gray blocks use the TX soft bonding logic and RX deskew
logic. The white blocks are your test logic or MAC layer logic.
9. Simulate your design to verify its functionality.
Figure 29. 12 Lanes Bonded Interlaken Link, TX Direction
To show more details, three different time segments are shown with the same zoom level.
tx_enh_frame_burst_en[0]
Send Feedback
Reset
Controller
Control and Status
Pattern
Generator
Control and Status
Pattern
Verifier
tx_ready Pre-Fill
Asserted Stage
pll_locked
tx_analogreset
12`h000
tx_clkout[0]
tx_clkout
tx_digitalreset
12`h000
tx_ready[0]
tx_ready
12`h... 12`hFFF
tx_enh_data_valid[0]
tx_enh_data_valid
12`h000 12`hFFF
tx_enh_fifo_full
12`h000
tx_enh_frame[0]
tx_enh_frame
12`h000 12`h000
tx_enh_frame_burst_en
12`hFFF 12`h000
tx_parallel_data
768'h<192_data_char>
tx_control
36'h<9_kl_char>
tx_enh_fifo_empty 12`hFFF 12`h000
tx_enh_fifo_pempty 12`hFFF 12`h000
PLL and CGB Reset
TX/RX Analog/Digital Reset
TX FIFO Status
TX Soft
TX FIFO Control
Bonding
TX Data Stream
RX FIFO Status
RX
Deskew
RX FIFO Control
RX Data Stream
Pre-Fill Completed
Assert burst_en for
All Lanes
12`h000
12`h000
12`hFFF
12`... 12`h000
12`hFFF 12`hFFF
12`h000... 12`h000
12`h000
768'h<192_data_char>
36'h<9_kl_char>
12`h000
12`h000
®
Intel Cyclone
PLL IP
TX Clocks
Cyclone 10
Transceiver
Native PHY
Send Data
Based on
FIFO Flags
12`h000
12`h000
12`hFFF
12`h000 12`hFFF 12`h000
12`hFFF 12`h000
12`h000
12`hFFF
768'h<192_data_char> 768`h...
36'h<9_kl_char>
12`h000
12`h000
®
10 GX Transceiver PHY User Guide
81