Intel Cyclone 10 GX User Manual page 59

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Table 50. Gearbox
Name
rx_bitslip[<n>-1:0]
tx_enh_bitslip[<n>-1:0
]
2.4.9.1. Enhanced PCS TX and RX Control Ports
This section describes the
protocol configurations.
When Enable simplified data interface is ON, all of the unused ports shown in the
tables below, appear as a separate port. For example: It appears as
unused_tx_control
Enhanced PCS TX Control Port Bit Encodings
Table 51. Bit Encodings for Interlaken
Name Bit
[1:0]
tx_control
[2]
[7:3]
[8]
[17:9]
Table 52. Bit Encodings for 10GBASE-R
Name
tx_control
Send Feedback
Direction Clock Domain
Input
rx_clkout
Input
rx_clkout
tx_control
/
unused_rx_control
Functionality
Synchronous header
Inversion control
Unused
Insert synchronous header error or
CRC32
Unused
Bit
[0] XGMII control signal for
[1]
XGMII control signal for
[2]
XGMII control signal for
[3]
XGMII control signal for
[4] XGMII control signal for
[5]
XGMII control signal for
[6]
XGMII control signal for
[7]
XGMII control signal for
[17:8] Unused
Description
The slips 1 bit for every positive edge
rx_parallel_data
of the input. Keep the minimum interval
rx_bitslip
between pulses to at least 20 cycles. The
rx_bitslip
maximum shift is < pcswidth -1> bits, so that if the PCS is
64 bits wide, you can shift 0-63 bits.
The value of this signal controls the number of bits to slip
the before passing to the PMA.
tx_parallel_data
and bit encodings for different
rx_control
port.
Description
The value 2'b01 indicates a data word. The value
2'b10 indicates a control word.
A logic low indicates that the built-in disparity
generator block in the Enhanced PCS maintains
the Interlaken running disparity.
You can use this bit to insert synchronous header
error or CRC32 errors. The functionality is similar
to . Refer to
tx_err_ins
description for more details.
Functionality
parallel_data[7:0]
parallel_data[15:8]
parallel_data[23:16]
parallel_data[31:24]
parallel_data[39:32]
parallel_data[47:40]
parallel_data[55:48]
parallel_data[63:56]
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
signal
tx_err_ins
59