Intel Cyclone 10 GX User Manual page 248

a. Assert
pll_cal_busy
b. Deassert
c.
Deassert
you deassert
2. The
pll_locked
minimum of 70 μs after deasserting
pll_locked
3. Deassert
tx_digitalreset
duration after
Note: You must reset the PCS blocks by asserting
Figure 149. Transmitter Reset Sequence During Device Operation
Related Information
Cyclone 10 GX Device Datasheet
4.3.1.1.2. Resetting the Receiver During Device Operation
Follow this reset sequence to reset the analog or digital blocks of the receiver at any
point during the device operation. Use this reset to re-establish a link or after dynamic
reconfiguration.
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
248
tx_analogreset
and
tx_cal_busy
pll_powerdown
tx_analogreset
pll_powerdown
signal goes high after the TX PLL acquires lock. Wait for a
signal.
tx_digitalreset
signal must stay asserted for a minimum
tx_analogreset
you assert
pll_powerdown
Device Power Up
pll_cal_busy
tx_cal_busy
tx_analogreset
pll_powerdown
pll_locked
tx_digitalreset
t req = 70 μs
1
Note:
(1) The Cyclone 10 GX Default setting presets tx_digitalreset to 70 μs.
(2) Area in gray is don't care logic state.
, , and
pll_powerdown
are low.
after a minimum duration of 70 μs.
. This step can be done at the same time or after
.
tx_analogreset
, after goes high. The
pll_locked
is deasserted.
tx_digitalreset
and
tx_analogreset
t t
req req
2
4. Resetting Transceiver Channels
UG-20070 | 2018.09.24
while
tx_digitalreset
to monitor the
t
tx_digitalreset
, every time
.
(1)
t
tx_digitalreset
3
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