Pci Express (Pipe) - Intel Cyclone 10 GX User Manual

Acronym
MAC
MII
OSI
PCS
PHY
PMA
PMD
SGMII
WAN
XAUI

2.7. PCI Express (PIPE)

You can use Cyclone 10 GX transceivers to implement a complete PCI Express solution
for Gen1 and Gen2 at data rates of 2.5 and 5.0 Gbps, respectively.
Configure the transceivers for PCIe functionality using one of the following methods:
• Cyclone 10 GX Hard IP for PCIe
This is a complete PCIe solution that includes the Transaction, Data Link, and
PHY/MAC layers. The Hard IP solution contains dedicated hard logic, which
connects to the transceiver PHY interface.
• Native PHY IP Core in PIPE Gen1/Gen2 Transceiver Configuration Rules
Use the Native PHY IP Core to configure the transceivers in PCIe mode, giving
access to the PIPE interface (commonly called PIPE mode in transceivers). This
mode enables you to connect the transceiver to a third-party MAC to create a
complete PCIe solution.
The PIPE specification (version 2.0) provides implementation details for a PCIe-
compliant physical layer. The Native PHY IP Core for PIPE Gen1 and Gen2 supports
x1, x2 or x4 operation for a total aggregate bandwidth ranging from 2 to 16 Gbps.
In a x1 configuration, the PCS and PMA blocks of each channel are clocked and
reset independently. The x2 and x4 configurations support channel bonding for
two-lane and four-lane links. In these bonded channel configurations, the PCS and
PMA blocks of all bonded channels share common clock and reset signals.
Gen1 and Gen2 modes use 8B/10B encoding, which has a 20% overhead to overall
link bandwidth. Gen1 and Gen2 modes use the Standard PCS, for its operation.
Table 117. Transceiver Solutions
Support
Gen1 and Gen2 data rates
MAC, data link, and transaction layer
Transceiver interface
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
122
Media Access Control.
Media independent interface.
Open System Interconnection.
Physical Coding Sublayer.
Physical Layer in OSI 7-layer architecture, also in Intel device scope is: PCS + PMA.
Physical Medium Attachment.
Physical Medium Dependent.
Serial Gigabit Media Independent Interface.
Wide Area Network.
10 Gigabit Attachment Unit Interface.
Cyclone 10 GX Hard IP for PCI
Hard IP through PIPE 2.0 based
interface
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
Definition
Native PHY IP Core for PCI Express
Express
Yes
Yes User implementation in FPGA fabric
•
UG-20070 | 2018.09.24
(PIPE)
Yes
PIPE 2.0 for Gen1 and Gen2
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