Intel Cyclone 10 GX User Manual page 168

Figure 84. Transceiver Channel Datapath and Clocking for Basic Configuration with Low
Latency Enabled
The clocking calculations in this figure are for an example when the data rate is 1250 Mbps and the PMA width
is 10 bits.
625 MHz (2)
Notes:
1. The parallel clock (tx_clkout or rx_clkout) is calculated as data rate/PCS-PMA interface width = 1250/10 = 125 MHz.
When the Byte Serializer is set to Serialize x2 mode, tx_clkout and rx_clkout become 1250/20 = 62.5 MHz.
2. The serial clock is calculated as data rate/2. The PMA runs on a dual data rate clock.
In low latency modes, the transmitter and receiver FIFOs are always enabled.
Depending on the targeted data rate, you can optionally bypass the byte serializer and
deserializer blocks.
Related Information
Cyclone 10 GX Standard PCS Architecture
2.9.2.1. Word Aligner Manual Mode
To use this mode:
1. Set the RX word aligner mode to Manual (FPGA Fabric controlled).
2. Set the RX word aligner pattern length option according to the PCS-PMA
interface width.
3. Enter a hexadecimal value in the RX word aligner pattern (hex) field.
This mode adds
Enable rx_std_wa_patternalign port option to enable
rx_std_wa_patternalign
the word aligner one time.
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
168
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
Transmitter PMA
10
tx_clkout
125 MHz (1)
tx_pma_div_clkout
Receiver PMA
10
Parallel Clock
(Recovered)
rx_clkout
125 MHz (1)
tx_clkout
Parallel Clock
(From Clock
Divider)
Parallel Clock
Serial Clock
Parallel and Serial Clock
rx_patterndetect
. An active high on
PRBS
Generator
/2
/2
PRBS
Verifier
rx_pma_div_clkout
Clock Generation Block (CGB)
Clock Divider
Parallel and Serial Clock
on page 299
and
rx_syncstatus
rx_std_wa_patternalign
UG-20070 | 2018.09.24
Transmitter Standard PCS
FPGA
Fabric
16
tx_coreclkin
62.5 MHz (1)
tx_clkout
Receiver Standard PCS
16
rx_coreclkin
62.5 MHz (1)
rx_clkout or
tx_clkout
ATX PLL
CMU PLL
fPLL
Serial Clock
. You can select the
re-aligns
Send Feedback