Intel Cyclone 10 GX User Manual page 111

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Name
Selected TX PMA local clock
division factor for 2.5 GbE
Enable Altera Debug Master
Endpoint
Enable capability registers
Set user-defined IP identifier
Enable control and status
registers
Enable PRBS soft
accumulators
Related Information
Embedded Debug Features
2.6.3.3. Functional Description
The 1G/2.5G/5G/10G Multi-rate PHY Intel FPGA IP core for Intel Cyclone 10 GX
devices implements the 10M to 10Gbps Ethernet PHY in accordance with the IEEE
802.3 Ethernet Standard. This IP core handles the frame encapsulation and flow of
data between a client logic and Ethernet network via a 10M to 10GbE PCS and PMA
(PHY).
Send Feedback
Value
Note: This option is not available for Intel Cyclone 10
GX devices.
This parameter is the local clock division factor in the
,
1 2
2.5G mode. It is directly mapped to the Native PHY IP
Core GUI options.
Note: This option is not available for Intel Cyclone 10
GX devices.
On, Off Available in Native PHY and TX PLL IP parameter editors.
When enabled, the Altera Debug Master Endpoint
(ADME) is instantiated and has access to the Avalon-MM
interface of the Native PHY. You can access certain test
and debug functions using System Console with the
ADME. Refer to the Embedded Debug Features section
for more details about ADME.
On, Off Available in Native PHY and TX PLL IP parameter editors.
Enables capability registers. These registers provide
high-level information about the transceiver channel's/
PLL's configuration.
User-specified Available in Native PHY and TX PLL IP parameter editors.
Sets a user-defined numeric identifier that can be read
from the
registers are enabled.
On, Off Available in Native PHY and TX PLL IP parameter editors.
Enables soft registers for reading status signals and
writing control signals on the PHY/PLL interface through
the ADME or reconfiguration interface.
On, Off Available in Native PHY IP parameter editor only.
Enables soft logic to perform PRBS bit and error
accumulation when using the hard PRBS generator and
checker.
on page 353
Description
offset when the capability
user_identifier
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
111