Timing Closure Recommendations; Plls And Clock Networks Revision History - Intel Cyclone 10 GX User Manual

3. PLLs and Clock Networks
UG-20070 | 2018.09.24
• Set the fPLL Mode to Cascade Source.
• Set the Desired output clock frequency.
3. Instantiate the fPLL IP core (the second PLL in PLL cascading configuration).
4. Configure the second fPLL IP core for the desired data rate and the reference clock
frequency. Set reference clock frequency for the second fPLL same as the output
frequency of the first fPLL.
5. Connect the fPLL IP core (cascade source) to fPLL IP core (transceiver PLL) as
shown in the above figure. Ensure the following connections:
•
The fPLL has an output port
the second fPLL's
6. Set the source (upstream) fPLL bandwidth to Low setting and the destination
(downstream) fPLL bandwidth to High setting.
7. If the input reference clock is available at device power-up, the first PLL will be
calibrated during the power-up calibration. The second PLL need to be
recalibrated. Refer to the User Recalibration section. If the input reference clock is
not available at device power-up, then re-run the calibration for the first PLL. After
the first PLL has been calibrated, re-calibrate the second PLL.
Note: No special configuration is required for the Native PHY instance.
Related Information
User Recalibration

3.11.4. Timing Closure Recommendations

Register mode is harder to close timing in Cyclone 10 GX devices. Intel recommends
using negative edge capture on the RX side for periphery to core transfers greater
than 240 MHz. To be specific, capture on a negative edge clock in the core and then
immediately transfer to a positive edge clock.
• Use PCLK clock network for frequencies up to 250 MHz.
• Local routing is recommended for higher frequencies.
For core to periphery transfers on TX targeting higher frequencies (beyond 250 MHz),
Intel recommends using TX Fast Register mode as the PCS FIFO mode. This is the
mode with PCLK that should be used by default for most 10GbE 1588 modes.
• You can use local routing to get up to 320 MHz in Register mode for the highest
speed grade.

3.12. PLLs and Clock Networks Revision History

Document
Version
2017.11.06 Made the following changes:
Send Feedback
hssi_pll_cascade_clk
port.
pll_refclk0
on page 383
. Connect this port to
Changes
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
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