Intel Cyclone 10 GX User Manual page 293

5. Cyclone 10 GX Transceiver PHY Architecture
UG-20070 | 2018.09.24
5.2.2.4. Descrambler
The descrambler block descrambles received data to regenerate unscrambled data
using the x
mode or synchronous mode.
Related Information
Scrambler
5.2.2.5. Interlaken Frame Synchronizer
The Interlaken frame synchronizer delineates the metaframe boundaries and searches
for each of the framing layer control words: Synchronization, Scrambler State, Skip,
and Diagnostic. When four consecutive synchronization words have been identified,
the frame synchronizer achieves the frame locked state. Subsequent metaframes are
then checked for valid synchronization and scrambler state words. If four consecutive
invalid synchronization words or three consecutive mismatched scrambler state words
are received, the frame synchronizer loses frame lock. In addition, the frame
synchronizer provides
FPGA fabric.
Note: The Interlaken frame synchronizer is available to implement the Interlaken protocol.
5.2.2.6. 64B/66B Decoder and Receiver State Machine (RX SM)
The 64B/66B decoder reverses the 64B/66B encoding process. The decoder block also
contains a state machine (RX SM) designed in accordance with the IEEE802.3-2008
specification. The RX SM checks for a valid packet structure in the data sent from the
remote side. It also performs functions such as sending local faults to the Media
Access Control (MAC)/Reconciliation Sublayer (RS) under reset and substituting error
codes when the 10GBASE-R and 10GBASE-KR PCS rules are violated.
Note: The 64B/66B decoder is available to implement the 10GBASE-R protocol.
5.2.2.6.1. PRBS Checker
You can use Cyclone 10 GX pseudo-random bit stream (PRBS) checker to easily
characterize high-speed links without developing or fully implementing any upper layer
of a protocol stack. The PRBS checker in Cyclone 10 GX devices is a shared hardened
block between the Standard and Enhanced datapaths. Hence, there is only one set of
control signals and registers for this feature.
You can use the PRBS checker block to verify the pattern generated by the PRBS
generator. The PRBS checker can be configured for two widths of the PCS-PMA
interface: 10 bits and 64 bits. PRBS9 is available in both 10-bit and 64-bit PCS-PMA
widths. All other PRBS patterns are available in 64-bit PCS-PMA width only. The PRBS
checker patterns can only be used when the PCS-PMA interface width is configured to
10 bits or 64 bits.
The pseudo-random bit stream (PRBS) block verifies the pattern generated by the
PRBS generator. The verifier supports the 64-bit PCS-PMA interface. PRBS7 supports
64-bit width only. PRBS9 supports 10-bit PMA data width to allow testing at a lower
data rate.
Send Feedback
58 39
+ x +1 polynomial. Like the scrambler, it operates in asynchronous
on page 290
rx_enh_frame_lock
(receiver metaframe lock status) to the
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Intel Cyclone 10 GX Transceiver PHY User Guide
293