Pcs Direct; Dynamic Reconfiguration Parameters - Intel Cyclone 10 GX User Manual

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Parameter
Enable RX polarity
inversion
Enable rx_polinv port
Enable rx_std_signaldetect
port
Table 31. PCIe Ports
Parameter
Enable PCIe dynamic
datarate switch ports
Enable PCIe
pipe_hclk_in and
pipe_hclk_out ports
Enable PCIe electrical
idle control and status
ports
Enable PCIe
pipe_rx_polarity port

2.4.6. PCS Direct

Table 32. PCS Direct Datapath Parameters
Parameter
PCS Direct interface width

2.4.7. Dynamic Reconfiguration Parameters

Dynamic reconfiguration allows you to change the behavior of the transceiver channels
and PLLs without powering down the device. Each transceiver channel and PLL
includes an Avalon-MM slave interface for reconfiguration. This interface provides
direct access to the programmable address space of each channel and PLL. Because
each channel and PLL includes a dedicated Avalon-MM slave interface, you can
Send Feedback
Range
On / Off
When you turn on this option, the
the polarity of RX parallel data. When you turn on this
parameter, you also need to enable Enable rx_polinv port.
On / Off
When you turn on this option, the
You can use this control port to swap the positive and negative
signals of a serial differential link if they were erroneously
swapped during board layout.
On / Off When you turn on this option, the optional
rx_std_signaldetect
required for the PCI Express protocol. If enabled, the signal
threshold detection circuitry senses whether the signal level
present at the RX input buffer is above the signal detect
threshold voltage that you specified. You can specify the signal
detect threshold using a Quartus Prime Assignment Editor or by
modifying the Quartus Settings File (.qsf)
Range
On / Off
When you turn on this option, the
pipe_sw_done
to the PLL IP core instance in multi-lane PCIe Gen2 configurations.
The
pipe_sw
multi-lane bonded configurations.
On / Off
When you turn on this option, the
pipe_hclk_out
connected to the PLL IP core instance for the PCI Express
configurations.
On / Off
When you turn on this option, the
pipe_rx_elecidle
PCI Express configurations.
On / Off
When you turn on this option, the
control port is enabled. You can use this option to control channel
signal polarity for PCI Express configurations. When the Standard
PCS is configured for PCIe, the assertion of this signal inverts the
RX bit polarity. For other Transceiver configuration rules the
optional
Range
8, 10, 16, 20, 32, 40, 64
Description
rx_std_polinv
rx_polinv
output port is enabled. This signal is
Description
pipe_rate
ports are enabled. You should connect these ports
and ports are only available for
pipe_sw_done
pipe_hclk_in
ports are enabled. These ports must be
pipe_rx_eidleinfersel
ports are enabled. These ports are used for
pipe_rx_polarity
port inverts the polarity of the RX bit stream.
rx_polinv
Description
Specifies the data interface width between the PLD and
the transceiver PMA.
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
port inverts
input is enabled.
, , and
pipe_sw
, and
and
input
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