Intel Cyclone 10 GX User Manual page 255

4. Resetting Transceiver Channels
UG-20070 | 2018.09.24
Note:
tx_analog_reset_ack
asynchronous signals. You must pass them through a synchronizer before sending
them to control logic.
4.3.2.1. Recommended Reset Sequence
4.3.2.1.1. Resetting the Transmitter During Device Operation
The numbers in this list correspond to the numbers in the following figure.
1. Assert
pll_cal_busy
2. Wait for
tx_analogreset
completed the reset request for assertion.
a. Deassert
b. Deassert
you deassert
3. Wait for
tx_analogreset
completed the reset request for deassertion.
4. The
pll_locked
tx_analogreset_ack
5. Deassert
goes high.
Figure 157. Transmitter Reset Sequence During Device Operation
Send Feedback
and
rx_analog_reset_ack
,
tx_analogreset pll_powerdown
and
tx_cal_busy
tx_analogreset_ack
.
tx_analogreset_ack
pll_powerdown
tx_analogreset
pll_powerdown
tx_analogreset_ack
.
tx_analogreset_ack
signal goes high after the TX PLL acquires lock. Wait for
to go low before monitoring the
tx_digitalreset
Device Power Up
pll_cal_busy
tx_cal_busy
tx_analogreset
tx_analogreset_ack
pll_powerdown
pll_locked
tx_digitalreset
Note:
(1) Area in gray is don't care logic state.
must be treated as
, and
tx_digitalreset
are low.
to go high, to ensure successful assertion of
goes high when TRS has successfully
after t .
pll_powerdown
. This step can be done at the same time or after
.
to go low, to ensure successful deassertion of
goes low when TRS has successfully
a minimum
t
tx_digitalreset
1 2 3 4
®
Intel Cyclone
, while
signal.
pll_locked
time after
pll_locked
t
tx_digitalreset
5
®
10 GX Transceiver PHY User Guide
255