Enabling And Disabling Loopback Modes Using Direct Reconfiguration Flow - Intel Cyclone 10 GX User Manual

6. Reconfiguration Interface and Dynamic Reconfiguration
UG-20070 | 2018.09.24
Table 187. Register Map for CTLE Settings
CTLE Feature
DC Gain
CTLE AC Gain Four
Stage
VGA SEL
Related Information
• Steps to Perform Dynamic Reconfiguration
• Cyclone 10 GX PMA Architecture
6.12.3. Enabling and Disabling Loopback Modes Using Direct
Reconfiguration Flow
Cyclone 10 GX devices have three loopback modes:
• Serial Loopback
• Reverse Serial Loopback (Pre-CDR)
• Reverse Serial Loopback (Post-CDR)
The loopback mode can be dynamically reconfigured by accessing the register space.
Serial Loopback Mode
In serial loopback mode, a path exists between the serializer of the transmitter and
the CDR of the receiver, so that the data from the CDR is recovered from the serializer
while the data from the receiver serial input pin is ignored. You can enable or disable
this mode.
Figure 214. Serial Loopback Mode
Send Feedback
Address Bits
0x11C, [3:0], [7:0]
0x11A
0x167 [5:1]
0x160 [3:1]
Transmitter
PCS
Receiver
PCS
Values
12'b000000000000
12'b111000000000
12'b111111000000
12'b111111111000
12'b111111111111
5'b00000 – 5'b11100
3'b000 – 3'b100
on page 328
on page 272
PMA
Serializer
Serial Loopback
PMA
Deserializer CDR
®
Intel Cyclone
Description
Sets the DC gain values. This
register can only be controlled when
in Four stage mode.
Sets the AC gain value when four
stage mode (High gain mode) is
selected.
Sets the VGA Gain value
®
10 GX Transceiver PHY User Guide
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