Intel Cyclone 10 GX User Manual page 324

Refer to Steps to Perform Dynamic Reconfiguration for a complete list of steps to
perform dynamic reconfiguration using the IP guided reconfiguration flow with
embedded streamer enabled. To perform a PMA reconfiguration such as TX PLL
switching, CGB divider switching, or reference clock switching, use the reconfiguration
flow for special cases described in Steps to Perform Dynamic Reconfiguration.
Table 177. Control and Status Register Memory Map for Embedded Reconfiguration
Streamer in Native PHY IP
Reconfigur Reconfigur
ation ation Bit
Address
(hex)
340 7
6
[2:0]
341 0
You can write to the address 0x340 at the same time to start the streaming, enable
broadcasting, and select the profile to be streamed. Different requests to multiple
channels can be made simultaneously by writing to the addresses of the desired
channels through the user reconfiguration interface (shared or independent). The
reconfig_waitrequest
streaming is complete.
Related Information
• Steps to Perform Dynamic Reconfiguration
• Analog Parameter Settings
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
324
Attribute Attribute
Name Description
cfg_load Start
streaming
bcast_en Broadcast
enable
cfg_sel Configuration
profile select
rcfg_busy Busy Status
bit
signal will remain asserted after the reconfiguration
on page 388
6. Reconfiguration Interface and Dynamic Reconfiguration
Bit Transceiver Block
Encoding
1'b1 Embedded
Reconfiguration
Streamer
1'b1 Embedded
Reconfiguration
Streamer
Direct Embedded
mapped Reconfiguration
Streamer
1'b1 Embedded
Reconfiguration
Streamer
on page 328
UG-20070 | 2018.09.24
Description
Set to 1'b1 to initiate
streaming, self-clearing bit
Set to 1'b1 to broadcast
the same profile to all the
channels
Binary encoding of the
configuration Profile to
stream
Bit is set to:
• 1'b1—streaming is in
progress
• 1'b0—streaming is
complete
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