Word Aligner In Manual Mode For Cpri - Intel Cyclone 10 GX User Manual

Figure 72. Word Aligner in Deterministic Mode Waveform
rx_std_wa_patternalign
rx_parallel_data
rx_patterndetect
Related Information
Word Aligner
2.8.2.1.1. Transmitter and Receiver Latency
The latency variation from the link synchronization function (in the word aligner block)
is deterministic with the
can use the
latency for port implementation in the remote radio head to compensate for latency
variation in the word aligner block. The
available to control the number of bits to be slipped in the transmitter serial data
stream. You can optionally use the
round-trip latency to a whole number of cycles.
When using the byte deserializer, additional logic is required in the FPGA fabric to
determine if the comma byte is received in the lower or upper byte of the word. The
delay is dependent on the word in which the comma byte appears.
Note: Latency numbers are pending device characterization.

2.8.3. Word Aligner in Manual Mode for CPRI

When configuring the word aligner in CPRI (Manual), the word aligner parses the
incoming data stream for a specific alignment character. After
deasserts, asserting the
for the predefined word alignment pattern or its complement in the received data
stream. It is important to note that the behavior of the word aligner in Manual mode
operates in different ways depending on the PCS-PMA interface width.
Table 134. Word Aligner Signal Status Behaviors in Manual Mode
PCS-PMA Interface Width
10
20
PCS-PMA Width = 10
When the PCS-PMA interface width is 10, 3 consecutive word alignment patterns found
after the initial word alignment in a different word boundary causes the word aligner
to resynchronize to this new word boundary if the
remains asserted;
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
152
rx_clkout
f1e4b6e4 b9dbf1db 915d061d
rx_errdetect 1101 0000 1010
rx_disperr
1101 0000 1010
0000
rx_syncstatus
0000
on page 305
rx_bitslipboundaryselectout
tx_bitslipboundaryselect
rx_std_wa_patternalign
rx_std_wa_patternali
Behavior
Level sensitive
Edge sensitive
rx_std_wa_patternalign
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
e13f913f 7a4ae24a bbae9b10
1000 0010 1010
1000 0000 1010
port to fix the round trip transceiver
tx_bitslipboundaryselect
tx_bitslipboundaryselect
triggers the word aligner to look
gn Behavior
rx_syncstatus
One parallel clock cycle (When
three control patterns are
detected)
Remains asserted until next
rising edge of
rx_std_wa_patternalign
rx_std_wa_patternalign
is level sensitive. If you deassert
UG-20070 | 2018.09.24
bcbcbcbc 95cd3c50 91c295cd
0000
0000
1111 0000
1111
port. Additionally, you
port is
port to round the
rx_digitalreset
rx_patterndetect
Behavior
One parallel clock cycle
One parallel clock cycle
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