How To Place Channels For Pipe Configurations - Intel Cyclone 10 GX User Manual

2.7.11. How to Place Channels for PIPE Configurations

Instead of the fitter or software model, the hardware dictates all the placement
restrictions. The restrictions are listed below:
• The channels must be contiguous for bonded designs.
• The master CGB is the only way to access x6 lines and must be used in bonded
designs. The local CGB cannot be used to route clock signals to slave channels
because the local CGB does not have access to x6 lines.
For ATX PLL placement restrictions, refer to the section "Transmit PLL
Recommendations Based on Data Rates" of PLLs and Clock Networks chapter.
Related Information
PLLs and Clock Networks
2.7.11.1. Master Channel in Bonded Configurations
For PCIe, both the PMA and PCS must be bonded. There is no need to specify the PMA
Master Channel because of the separate Master CGB in the hardware. However, you
must specify the PCS Master Channel through the Native PHY. You can choose any one
of the data channels (part of the bonded group) as the logical PCS Master Channel.
Note: Whichever channel you pick as the PCS master, the fitter will select physical CH1 or
CH4 of a transceiver bank as the master channel. This is because the Auto-Speed
Negotiation (ASN) block and Master CGB connectivity only exists in the hardware of
these two channels of the transceiver bank.
Table 130. Logical PCS Master Channel for PIPE Configuration
PIPE Configuration
x1
x2
x4
(24)
Ensure that the Logical PCS Master Channel aligns with Physical Channel 1 or 4 in a given
transceiver bank.
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
146
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
on page 198
Logical PCS Master Channel # (default)
UG-20070 | 2018.09.24
(24)
0
(24)
1
(24)
2
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