Xcvr_C10_Tx_Term_Sel; Xcvr_C10_Tx_Compensation_En - Intel Cyclone 10 GX User Manual

8.6.1. XCVR_C10_TX_TERM_SEL

Pin planner or Assignment Editor Name
Transmitter On-Chip Termination
Description
Controls the on-chip TX differential termination for different protocols.
Table 222. Available Options
Value
R_R1
R_R2
Note: When the data rate is less than or equal to 12.5 Gbps, the default value is R_R1.

8.6.2. XCVR_C10_TX_COMPENSATION_EN

Pin planner or Assignment Editor Name
Transmitter High-Speed Compensation
Description
Specifies if the power distribution network (PDN) induced inter-symbol interference
(ISI) compensation is enabled or disabled in the TX driver. When enabled, it reduces
the PDN induced ISI jitter, but increases the power consumption. Use this feature for
high speed applications. It defaults to ENABLE for non-PCIe modes.
Table 223. Available Options
Value
ENABLE
DISABLE
Table 224. Rules
Data Rate
PCIe Gen1, Gen2
Others
Assign To
TX serial data pin.
Syntax
set_instance_assignment -name XCVR_C10_TX_COMPENSATION_EN <value>
-to <tx_serial_data pin name>
Related Information
EPE (Early Power Estimator)
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
394
100 Ohm
85 Ohm
Compensation ON
Compensation OFF
Value of XCVR_C10_TX_COMPENSATION_EN
DISABLE
ENABLE/DISABLE
8. Analog Parameter Settings
UG-20070 | 2018.09.24
Description
Description
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