Calibration Registers; Avalon-Mm Interface Arbitration Registers - Intel Cyclone 10 GX User Manual

7. Calibration
UG-20070 | 2018.09.24
calibration is done. If you write 0x2 to 0x0 during calibration, PreSICE can stop the
calibration process and return the internal configuration bus back to you; therefore,
calibration is not done while the
tx_cal_busy
separated from the hardware. Configure the capability register 0x281[5:4] to enable
or disable
reconfiguration interface.
Related Information
• Arbitration
• Avalon Interface Specifications
• Reconfiguration Interface and Dynamic Reconfiguration Chapter

7.2. Calibration Registers

The Cyclone 10 GX transceiver PMA and PLLs include the following types of registers
for calibration:
•

Avalon-MM interface arbitration registers

• Calibration enable registers
• Capability registers
• Rate switch flag registers
The Avalon-MM interface arbitration registers enable you to request internal
configuration bus access.
The PMA and PLL calibration enable registers for user recalibration are mapped to
offset address 0x100. All calibration enable registers are self-cleared after the
calibration process is completed.
The
tx_cal_busy
pll_cal_busy
The rate switch flag registers are only used for CDR rate change.
7.2.1. Avalon-MM Interface Arbitration Registers
Table 206. Avalon-MM Interface Arbitration Registers
Bit
[0]
[1]
(32)
The transceiver channel, ATX PLL, and fPLL use the same offset address.
Send Feedback
reconfig_waitrequest
and
rx_cal_busy
or
tx_cal_busy rx_cal_busy
on page 325
,
rx_cal_busy
signals are available from the capability registers.
Offset Address
(32)
0x0
0x0
are from the same internal node which cannot be
individually through the Avalon-MM
, ATX PLL
pll_cal_busy
Description
This bit arbitrates the control of Avalon-MM interface.
• Set this bit to 0 to request control of the internal configuration
bus by user.
• Set this bit to 1 to pass the internal configuration bus control to
PreSICE.
This bit indicates whether or not calibration is done. This is the
inverted signal. You can write to this bit; however, if
cal_busy
you accidentally write 0x0 without enabling any calibration bit in
®
Intel Cyclone
is low. The PMA
on page 315
, and fPLL
continued...
®
10 GX Transceiver PHY User Guide
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