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Summary of Contents for Intel Cyclone 10 GX

Page 1 ® ® Intel Cyclone 10 GX Transceiver PHY User Guide ® ® Updated for Intel Quartus Prime Design Suite: 18.1 Subscribe UG-20070 | 2018.09.24 Send Feedback Latest document on the web: HTML...
Page 2: Table Of Contents
1.2.3. Transceiver Phase-Locked Loops..............13 1.2.4. Clock Generation Block (CGB)..............14 1.3. Calibration......................14 1.4. Intel Cyclone 10 GX Transceiver PHY Overview Revision History......... 15 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers........16 2.1. Transceiver Design IP Blocks................. 16 2.2.
Page 3 2.7.2. Supported PIPE Features................. 123 2.7.3. How to Connect TX PLLs for PIPE Gen1 and Gen2 Modes......128 2.7.4. How to Implement PCI Express (PIPE) in Cyclone 10 GX Transceivers... 131 2.7.5. Native PHY IP Parameter Settings for PIPE ..........131 2.7.6.
Page 4 5.3. Cyclone 10 GX Standard PCS Architecture............299 5.3.1. Transmitter Datapath................300 5.3.2. Receiver Datapath.................. 305 5.4. Intel Cyclone 10 GX Transceiver PHY Architecture Revision History......314 6. Reconfiguration Interface and Dynamic Reconfiguration .......... 315 6.1. Reconfiguring Channel and PLL Blocks..............315 6.2. Interacting with the Reconfiguration Interface............316 ®...
Page 5 6.16.2. Using Pseudo Random Pattern Mode............368 6.17. Timing Closure Recommendations..............369 6.18. Unsupported Features..................371 6.19. Cyclone 10 GX Transceiver Register Map.............372 6.20. Reconfiguration Interface and Dynamic Reconfiguration Revision History....372 7. Calibration........................373 7.1. Reconfiguration Interface and Arbitration with PreSICE Calibration Engine ....373 7.2.
Page 6 8.8. Transmitter VOD Settings..................400 8.8.1. XCVR_C10_TX_VOD_OUTPUT_SWING_CTRL..........400 8.9. Dedicated Reference Clock Settings..............401 8.9.1. XCVR_C10_REFCLK_TERM_TRISTATE............401 8.9.2. XCVR_C10_TX_XTX_PATH_ANALOG_MODE..........401 8.10. Unused Transceiver Channels Settings..............402 8.11. Analog Parameter Settings Revision History............402 ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 7: Intel ® Cyclone ® 10 Gx Transceiver Phy Overview
Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 8: Device Transceiver Layout
Figure 1. Intel Cyclone 10 GX FPGA Architecture Block Diagram The transceiver channels are placed on the left side periphery in Intel Cyclone 10 GX devices. 1.1.1. Intel Cyclone 10 GX Device Transceiver Layout Intel Cyclone 10 GX devices offer 6-, 10-, or 12-transceiver channel counts. Each transceiver bank has up to six transceiver channels.
Page 9 Legend: PCIe Gen1 - Gen2 Hard IP blocks with Configuration via Protocol (CvP) capabilities. Cyclone 10 GX device with 12 transceiver channels and one PCIe Hard IP block. Figure 3. Intel Cyclone 10 GX Devices with 10 Transceiver Channels and One PCIe Hard...
Page 10: Intel Cyclone 10 Gx Device Package Details
1.1.2. Intel Cyclone 10 GX Device Package Details The following tables list package sizes, available transceiver channels, and PCI Express Hard IP blocks for Intel Cyclone 10 GX devices. Table 1. Package Details for Devices with Transceivers and Hard IP Blocks Located on the Left Side Periphery of the Device •...
Page 11: Phy Layer Transceiver Components
Related Information PLLs and Clock Networks on page 198 1.2.2. PHY Layer Transceiver Components Transceivers in Intel Cyclone 10 GX devices support both Physical Medium Attachment (PMA) and Physical Coding Sublayer (PCS) functions at the physical (PHY) layer. ® ®...
Page 12 PCS Direct Notes: (1) The FPGA Fabric - PCS and PCS-PMA interface widths are configurable. Intel Cyclone 10 GX transceiver channels have three types of PCS blocks that together support continuous data rates between 1.0 Gbps and 10.81344 Gbps. Table 2.
Page 13: Transceiver Phase-Locked Loops
1. Intel Cyclone 10 GX Transceiver PHY Overview UG-20070 | 2018.09.24 1.2.3. Transceiver Phase-Locked Loops Each transceiver channel in Intel Cyclone 10 GX devices has direct access to three types of high performance PLLs: • Advanced Transmit (ATX) PLL •...
Page 14: Clock Generation Block (Cgb)
1. Intel Cyclone 10 GX Transceiver PHY Overview UG-20070 | 2018.09.24 1.2.4. Clock Generation Block (CGB) In Intel Cyclone 10 GX devices, there are two types of clock generation blocks (CGBs): • Master CGB • Local CGB Transceiver banks with six transceiver channels have two master CGBs. Master CGB1 is located at the top of the transceiver bank and master CGB0 is located at the bottom of the transceiver bank.
Page 15: Intel Cyclone 10 Gx Transceiver Phy Overview Revision History
Changed the description of the Fractional PLL in the "Fractional PLL (fPLL)" section. • Changed the location of the PCIe Hard IP block in the " Cyclone 10 GX Devices with 12 Transceiver Channels and One PCIe Hard IP Block" figure.
Page 16: Implementing Protocols In Intel Cyclone 10 Gx Transceivers
Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 17: Transceiver Design Flow
2.2.1. Select and Instantiate the PHY IP Core Select the appropriate PHY IP core to implement your protocol. Refer to the Cyclone 10 GX Transceiver Protocols and PHY IP Support section to decide which PHY IP to select to implement your protocol.
Page 18 1. Open the Quartus Prime software. 2. Click Tools IP Catalog. 3. At the top of the IP Catalog window, select Cyclone 10 GX device family 4. In IP Catalog, under Library Interface Protocols, select the appropriate PHY IP and then click Add.
Page 19: Configure The Phy Ip Core
To instantiate a PLL IP: 1. Open the Quartus Prime software. 2. Click Tools IP Catalog. 3. At the top of the IP Catalog window, select Cyclone 10 GX device family 4. In IP Catalog, under Library Basic Functions Clocks, PLLs, and Resets...
Page 20: Configure The Pll Ip Core
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 5. In the New IP Instance Dialog Box, provide the IP instance name. 6. Select Cyclone 10 GX device family. 7. Select the appropriate device and click OK.
Page 21: Generate The Pll Ip Core
IP Core File Locations on page 67 For more information about IP core file structure 2.2.7. Reset Controller There are two methods to reset the transceivers in Cyclone 10 GX devices: • Use the Transceiver PHY Reset Controller. • Create your own reset controller that follows the recommended reset sequence.
Page 22: Connect The Phy Ip To The Pll Ip Core And Reset Controller
Related Information • Resetting Transceiver Channels on page 243 • Using the Cyclone 10 GX Transceiver Native PHY IP Core on page 26 • PLLs and Clock Networks on page 198 2.2.10. Connect Datapath Connect the transceiver PHY layer design to the Media Access Controller (MAC) IP core or to a data generator / analyzer or a frame generator / analyzer.
Page 23 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Related Information Intel Quartus Prime Pro Edition Handbook Volume 3: Verification Information about design simulation and verification. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 24: Cyclone 10 Gx Transceiver Protocols And Phy Ip Support
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 2.3. Cyclone 10 GX Transceiver Protocols and PHY IP Support Table 3. Cyclone 10 GX Transceiver Protocols and PHY IP Support Protocol Transceiver PHY IP PCS Support Transceiver...
Page 25 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Protocol Transceiver PHY IP PCS Support Transceiver Protocol Preset Core Configuration Rule SONET/SDH STS-192/ Native PHY IP core Enhanced Basic (Enhanced PCS) User created STM-64 (10G) via SFP...
Page 26: Using The Cyclone 10 Gx Transceiver Native Phy Ip Core
2.4. Using the Cyclone 10 GX Transceiver Native PHY IP Core This section describes the use of the Intel-provided Cyclone 10 GX Transceiver Native PHY IP core. This Native PHY IP core provides direct access to Cyclone 10 GX transceiver PHY features.
Page 27 Although the Quartus Prime software provides legality checks, refer to the High-Speed Serial Transceiver-Fabric Interface Performance for Intel Cyclone 10 GX Devices section of theIntel Cyclone 10 GX Device Datasheet for the supported FPGA fabric to PCS interface widths and frequency.
Page 28: Presets
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 • 10GBASE-R and 10GBASE-R with IEEE 1588v2 Variants on page 98 • PCI Express (PIPE) on page 122 • CPRI on page 149 • Using the "Basic (Enhanced PCS)" Configuration on page 158 •...
Page 29 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Table 4. General, Common PMA Options, and Datapath Options Parameter Value Description Message level for rule error Specifies the messaging level for parameter rule violations. violations Selecting error causes all rule violations to prevent IP generation.
Page 30 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Parameter Value Description The default value is Off. Enable simplified data On/Off By default, all 128-bits are ports for the tx_parallel_data interface buses are exposed. You must understand the rx_parallel_data mapping of data and control signals within the interface.
Page 31: Pma Parameters
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 2.4.3. PMA Parameters You can specify values for the following types of PMA parameters: TX PMA • TX Bonding Options • TX PLL Options • TX PMA Optional Ports RX PMA •...
Page 32 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Table 7. TX PLL Options Parameter Value Description TX local clock division 1, 2, 4, 8 Specifies the value of the divider available in the transceiver factor channels to divide the TX PLL output clock to generate the correct frequencies for the parallel and serial clocks.
Page 33 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Parameter Value Description Use this feature when you want to dynamically re-configure CDR reference clock source. Selected CDR reference 0 to <number of Specifies the initial CDR reference clock. This parameter...
Page 34: Enhanced Pcs Parameters
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Parameters Value Description Enable rx_pma_clkslip On/Off Enables the optional control input port. A rising rx_pma_clkslip port edge on this signal causes the RX serializer to slip the serial data by one clock cycle, or 2 unit intervals (UI).
Page 35 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Parameter Range Description The 67-bit FPGA fabric to PCS interface width uses the 64-bits from the TX and RX parallel data. The block synchronizer determines the block boundary of the 67-bit word with lower 3 bits from the control bus.
Page 36 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Parameter Range Description Enable On / Off Enables the tx_enh_fifo_pfull port. This signal indicates when tx_enh_fifo_pfull port the TX FIFO reaches the specified partially full threshold. This signal is synchronous to...
Page 37 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Parameter Range Description Enable On / Off Enables the rx_enh_data_valid port. This signal indicates when rx_enh_data_valid port RX data from RX FIFO is valid. This signal is synchronous to rx_coreclkin.
Page 38 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Parameter Range Description Enable tx_enh_frame On / Off Enables the status output port. When the tx_enh_frame port Interlaken frame generator is enabled, this signal indicates the beginning of a new metaframe. This is an asynchronous signal.
Page 39 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Table 18. 10GBASE-R BER Checker Parameters Parameter Range Description Enable On / Off Enables the rx_enh_highber port. For 10GBASE-R transceiver rx_enh_highber port configuration rule, this signal is asserted to indicate a bit error...
Page 40 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Table 21. Interlaken Disparity Generator and Checker Parameters Parameter Range Description Enable Interlaken TX On / Off When you turn on this option, the Enhanced PCS enables the disparity generator disparity generator.
Page 41: Standard Pcs Parameters
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 • Using the "Basic (Enhanced PCS)" Configuration on page 158 2.4.5. Standard PCS Parameters This section provides descriptions of the parameters that you can specify to customize the Standard PCS.
Page 42 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Parameter Range Description Enable On / Off Enables the port. This signal indicates tx_std_pcfifo_empty tx_std_pcfifo_empty when the standard TX phase compensation FIFO is empty. This port signal is synchronous with...
Page 43 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Parameter Range Description RX rate match insert/ User-specified 20 bit Specifies the +ve (positive) disparity value for the RX rate match delete +ve pattern (hex) pattern FIFO as a hexadecimal string.
Page 44 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Parameter Range Description Enable rx_std_wa_a1a2size port On / Off Enables the optional control input rx_std_wa_a1a2size port. Enable On / Off Enables the optional status rx_std_bitslipboundarysel rx_std_bitslipboundarysel port output port.
Page 45: Pcs Direct
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Parameter Range Description Enable RX polarity On / Off When you turn on this option, the port inverts rx_std_polinv inversion the polarity of RX parallel data. When you turn on this parameter, you also need to enable Enable rx_polinv port.
Page 46 PLLs. For example, you can change the reference clock input to the TX PLL. You can also change between the Standard and Enhanced datapaths. To enable Intel Cyclone 10 GX transceiver toolkit capability in the Native PHY IP core, you must enable the following options: •...
Page 47 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Table 35. Configuration Files Parameter Value Description Configuration file <prefix> Here, the file prefix to use for generated configuration files is prefix specified. Each variant of the Transceiver Native PHY IP should use a unique prefix for configuration files.
Page 48 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Parameter Value Description Store Clicking this button saves or stores the current Native PHY parameter settings to the configuration profile specified by the Selected reconfiguration profile parameter. to selected...
Page 49 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Parameter Value Description Pre-Emphasis First Post-Tap Fir_post_1t_neg Selects the polarity of the first post-tap for pre- Polarity emphasis Fir_post_1t_pos (17) Pre-Emphasis First Post-Tap 0-25 Selects the magnitude of the first post-tap for pre- Magnitude emphasis.
Page 50: Pma Ports
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 2.4.8. PMA Ports This section describes the PMA and calibration ports for the Cyclone 10 GX Transceiver Native PHY IP core. The following tables, the variables represent these parameters: •...
Page 51 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Name Direction Clock Domain Description Output Clock This port is available if you turn on Enable tx_ tx_pma_iqtxrx_clko pma_iqtxrx_clkout port in the Transceiver Native PHY IP core Parameter Editor. This output clock can be used to cascade the TX PMA output clock to the input of a PLL.
Page 52 Input Asynchronous Resets the digital RX portion of the transceiver rx_digitalreset[<n>-1 PHY. (20) Although the reset ports are not synchronous to any clock domain, Intel recommends that you synchronize the reset ports with the system clock. ® ® Intel Cyclone...
Page 53: Enhanced Pcs Ports
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 2.4.9. Enhanced PCS Ports Figure 13. Enhanced PCS Interfaces The labeled inputs and outputs to the PMA and PCS modules represent buses, not individual signals. Cyclone 10 Transceiver Native PHY...
Page 54 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Name Direction Clock Domain Description For double width configuration, the following bits are active: • 40-bit FPGA fabric to PCS interface width: data[103:64], [39:0]. Ground [127:104], [63:40]. •...
Page 55 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Table 44. Enhanced RX PCS: Parallel Data, Control, and Clocks Name Direction Clock Domain Description Output Synchronous RX parallel data from the RX PCS to the FPGA fabric. If you rx_parallel_data[<n...
Page 56 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Name Direction Clock Domain Description Refer to Enhanced PCS FIFO Operation on page 164 for more details. Output Synchronous to Assertion of this signal indicates the TX FIFO is full.
Page 57 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Name Direction Clock Domain Description the FIFO Refer to Enhanced PCS FIFO Operation on page 164 for more details. rx_coreclkin rx_clkout Output Synchronous to When asserted, indicates that the RX FIFO is empty.
Page 58 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Name Direction Clock Domain Description frame generator block. This bus must be held constant for 5 clock cycles before and after the pulse. The tx_enh_frame following encodings are defined: •...
Page 59 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Table 50. Gearbox Name Direction Clock Domain Description Input slips 1 bit for every positive edge rx_bitslip[<n>-1:0] rx_clkout rx_parallel_data of the input. Keep the minimum interval rx_bitslip between pulses to at least 20 cycles.
Page 60 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Table 53. Bit Encodings for Basic Single Width Mode For basic single width mode, the total word length is 66-bit with 64-bit data and 2-bit synchronous header. Name...
Page 61 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Name Functionality Description SKIP word location A logic high (1'b1) indicates the SKIP word location in a metaframe. Diagnostic word location A logic high (1'b1) indicates the diagnostic word location in a metaframe.
Page 62: Standard Pcs Ports
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Name Functionality Description Synchronous header error status Active-high status signal that indicates a synchronous header error. Block lock is achieved Active-high status signal indicating when block lock is achieved.
Page 63 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 In the following tables, the variables represent these parameters: • <n>—The number of lanes • <w>—The width of the interface • <d>—The serialization factor • <s>— The symbol size •...
Page 64 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Table 63. Standard PCS FIFO Name Direction Clock Domain Description Output Synchronous Indicates when the standard TX FIFO is full. tx_std_pcfifo_full[<n to the clock >-1:0] driving the write side of...
Page 65 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Table 65. 8B/10B Encoder and Decoder Name Direction Clock Domain Description Input tx_clkout is exposed if 8B/10B enabled and simplified data tx_datak tx_datak interface is set.When 1, indicates that the 8B/10B encoded word of tx_parallel_data is control.
Page 66 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Name Direction Clock Domain Description . For each 128-bit word, rx_parallel_data corresponds to rx_patterndetect rx_parallel_data[12] Output Asynchronous When asserted, indicates that the conditions required for rx_syncstatus[<n><w>/ synchronization are being met.
Page 67: Ip Core File Locations
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Name Direction Clock Domain Description receive circuitry receives all words in the reverse order. The bit reversal circuitry operates on the output of the word aligner. Input Asynchronous When asserted, the TX polarity bit is inverted.
Page 68 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Figure 15. Directory Structure for Generated Files <Project Directory> <your_ip_or_system_name>.qsys - Top-level IP variation file <your_ip_or_system_name>.sopcinfo <your_ip_name> - IP core variation files <your_ip_name>.cmp - VHDL component declaration file <your_ip_name>_bb - Verilog HDL black-box EDA synthesis file...
Page 69: Unused Transceiver Channels
To prevent performance degradation of unused transceiver channels over time, the following assignments for RX pins must be added to an Cyclone 10 GX device QSF. You can either use a global assignment or per-pin assignment. For the per-pin assignment, true or complement RX pin can be specified.
Page 70: Interlaken
The Interlaken interface is supported with 1 to 12 lanes running at data rates up to 12.5 Gbps per lane on Cyclone 10 GX devices. Interlaken is implemented using the Enhanced PCS. The Enhanced PCS has demonstrated interoperability with Interlaken ASSP vendors and third-party IP suppliers.
Page 71: Metaframe Format And Framing Layer Control Word
2.5.1. Metaframe Format and Framing Layer Control Word The Enhanced PCS supports programmable metaframe lengths from 5 to 8192 words. However, for stability and performance, Intel recommends you set the frame length to no less than 128 words. In simulation, use a smaller metaframe length to reduce simulation times.
Page 72 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Figure 17. Framing Layer Metaframe Format Metaframe Length Control and Data Words The framing control words include: • Synchronization (SYNC)—for frame delineation and lane alignment (deskew) • Scrambler State (SCRM)—to synchronize the scrambler •...
Page 73: Interlaken Configuration Clocking And Bonding
32 31 2.5.2. Interlaken Configuration Clocking and Bonding The Cyclone 10 GX Interlaken PHY layer solution is scalable and has flexible data rates. You can implement a single lane link or bond up to 48 lanes together. You can choose a lane data rate up to 12.5 Gbps. You can also choose between different reference clock frequencies, depending on the PLL used to clock the transceiver.
Page 74 TX Channel TX Channel TX Channel TX Channel Note: Intel Cyclone 10 GX devices have transceiver channels that can support data rates up to 12.5 Gbps for chip-to-chip and chip-to-module communication, and up to 6.6 Gbps for backplane communication. Related Information •...
Page 75 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 required by the protocol. Based on these FIFO status and control signals, you can implement the multi-lane deskew alignment state machine in the FPGA fabric to control the transceiver RX FIFO block.
Page 76 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Figure 22. TX Soft Bonding Flow Exit from tx_digitalreset Deassert all lanes tx_enh_frame_burst_en Assert all lanes tx_enh_data_valid All lanes full? Deassert all lanes tx_enh_data_valid Any lane send new frame?
Page 77 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Figure 23. TX FIFO Pre-fill (6-lane Interface) Deassert tx_digitalreset tx_digitalreset tx_enh_data_valid tx_enh_fifo_full tx_enh_fifo_pfull tx_enh_fifo_empty tx_enh_fifo_pempty tx_enh_fifo_cnt 000000 1... 2... 3... 4... 5... 6... 7... 8... 9... a... b... c... d... e... ffffff...
Page 78 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Figure 25. State Flow of the RX FIFO Deskew Exit from rx_digitalreset Deassert all Lane’s rx_enh_fifo_rd_en All Lane’s rx_enh_fifo_pempty Deasserted? Assert rx_enh_fifo_align_clr for at least 4 rx_coreclkin Cycles All Lane’s...
Page 79: How To Implement Interlaken In Cyclone 10 Gx Transceivers
Cyclone 10 GX devices provide three preset variations for Interlaken in the IP Parameter Editor: • Interlaken 1x6.25 Gbps • Interlaken 6x10.3 Gbps 1. Instantiate the Cyclone 10 GX Transceiver Native PHY IP from the IP Catalog (Installed IP Library Interface Protocols Transceiver PHY Cyclone 10 GX Transceiver Native PHY).
Page 80 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Figure 27. Signals and Ports of Native PHY IP for Interlaken Cyclone 10 Transceiver Native PHY reconfig_reset tx_cal_busy Hard Reconfiguration reconfig_clk rx_cal_busy Calibration Block Registers reconfig_avmm TX PMA...
Page 81 This figure shows and example connection for an Interlake PHY design. For the blue blocks, Intel provides an IP core. The gray blocks use the TX soft bonding logic and RX deskew logic. The white blocks are your test logic or MAC layer logic.
Page 82: Native Phy Ip Parameter Settings For Interlaken
Based on FIFO Flags 2.5.4. Native PHY IP Parameter Settings for Interlaken This section contains the recommended parameter values for this protocol. Refer to Using the Cyclone 10 GX Transceiver Native PHY IP Core for the full range of parameter values. Table 69.
Page 83 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Parameter Value Actual PCS TX channel bonding master If TX channel bonding mode is set to PMA and PCS bonding, then: 0, 1, 2, 3,...,[Number of data channels – 1]...
Page 84 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Parameter Value Enable RX/TX FIFO double-width mode TX FIFO mode Interlaken TX FIFO partially full threshold 8 to 15 TX FIFO partially empty threshold 1 to 8 Enable tx_enh_fifo_full port...
Page 85 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Table 74. Interlaken Frame Synchronizer Parameters Parameter Value Enable Interlaken frame synchronizer Frame synchronizer metaframe length 5 to 8192 (Intel recommends a minimum metaframe length of 128) Enable rx_enh_frame port...
Page 86: Ethernet
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Parameter Value Enable RX data polarity inversion On / Off Enable tx_enh_bitslip port Enable rx_bitslip port Table 80. Dynamic Reconfiguration Parameters Parameter Value Enable dynamic reconfiguration On / Off...
Page 87: Gigabit Ethernet (Gbe) And Gbe With Ieee 1588V2
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Table 83. 1G/10G Data Rates and Transceiver Configuration Rules Data Rate Transceiver Configuration Rule/IP • Gigabit Ethernet • Gigabit Ethernet 1588 • 10GBASE-R • 10GBASE-R 1588 1G/10G 1G/10G Ethernet PHY IP 2.6.1.
Page 88 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Figure 32. Transceiver Channel Datapath and Clocking at 1250 Mbps for GbE, GbE with IEEE 1588v2 Transmitter PMA Transmitter Standard PCS FPGA Fabric PRBS tx_coreclkin Generator 625 MHz...
Page 89 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 For the GbE protocol, the transmitter replaces any /Dx.y/ following a /K28.5/ comma with either a /D5.6/ (/I1/ ordered set) or a /D16.2/ (/I2/ ordered set), depending on the current running disparity.
Page 90 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Figure 34. Reset Condition n + 1 n + 3 n + 2 n + 4 clock tx_digitalreset tx_parallel_data K28.5 K28.5 K28.5 K28.5 Dx.y Dx.y K28.5 Dx.y K28.5 Dx.y...
Page 91 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Figure 35. rx_syncstatus High Three Consecutive Ordered Sets Received to Achieve Synchronization rx_parallel_data rx_datak rx_syncstatus rx_patterndetect rx_disperr rx_errdetect Related Information Word Aligner on page 305 2.6.1.3. 8B/10B Decoding for GbE, GbE with IEEE 1588v2 The 8B/10B decoder takes a 10-bit encoded value as input and produces an 8-bit data value and 1-bit control value as output.
Page 92 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 2.6.1.4. Rate Match FIFO for GbE The rate match FIFO compensates frequency Part-Per-Million (ppm) differences between the upstream transmitter and the local receiver reference clock up to 125 MHz ±...
Page 93 Related Information Rate Match FIFO on page 310 2.6.1.5. How to Implement GbE, GbE with IEEE 1588v2 in Intel Cyclone 10 GX Transceivers You should be familiar with the Standard PCS and PMA architecture, PLL architecture, and the reset controller before implementing the GbE protocol.
Page 94 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Refer to Select and Instantiate the PHY IP Core on page 17. 2. Select GbE or GbE 1588 from the Transceiver configuration rules list located under Datapath Options, depending on which protocol you are implementing.
Page 95 2.6.1.6. Native PHY IP Parameter Settings for GbE and GbE with IEEE 1588v2 This section contains the recommended parameter values for this protocol. Refer to Using the Cyclone 10 GX Transceiver Native PHY IP Core for the full range of parameter values.
Page 96 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Table 86. TX PMA Parameters Parameter Value TX channel bonding mode Not bonded TX local clock division factor 1, 2, 4, 8 Number of TX PLL clock inputs per channel...
Page 97 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Parameters Value low latency (for GbE) RX FIFO mode register_fifo (for GbE with IEEE 1588v2) Enable tx_std_pcfifo_full port On/Off Enable tx_std_pcfifo_empty port On/Off Enable rx_std_pcfifo_full port On/Off Enable rx_std_pcfifo_empty port...
Page 98: 10Gbase-R And 10Gbase-R With Ieee 1588V2 Variants
2.6.2. 10GBASE-R and 10GBASE-R with IEEE 1588v2 Variants 10GBASE-R PHY is the Ethernet-specific physical layer running at a 10.3125-Gbps data rate as defined in Clause 49 of the IEEE 802.3-2008 specification. Cyclone 10 GX transceivers can implement 10GBASE-R variants like 10GBASE-R with IEEE 1588v2.
Page 99 • 10GBASE-R • 10GBASE-R Low Latency • 10GBASE-R Register Mode Intel recommends that you use the presets for selecting the suitable 10GBASE-R variants directly if you are configuring through the Native PHY IP core. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide...
Page 100 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Figure 44. Transceiver Channel Datapath and Clocking for 10GBASE-R Transmitter PMA Transmitter Enhanced PCS FPGA Fabric Data & Control 10.3125 Gbps 64 + 8 PRBS @ 156.25 MHz...
Page 101 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 The protocol is applicable to systems communicating by local area networks including, but not limited to, Ethernet. The protocol enables heterogeneous systems that include clocks of various inherent precision, resolution, and stability to synchronize to a grandmaster clock.
Page 102 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Figure 46. XGMII Interface (DDR) and Transceiver Interface (SDR) for 10GBASE-R Configurations XGMII Transfer (DDR) Interface Clock (156.25) MHz TXD/RXD[31:0] TXC/RXC[3:0] Transceiver Interface (SDR) Interface Clock (156.25) MHz...
Page 103 You must design your own MAC and other layers in the FPGA to implement the 10GBASE-R or 10GBASE-R with 1588 Transceiver Configuration Rule using the Native PHY IP. 1. Instantiate the Intel Cyclone 10 GX Transceiver Native PHY IP from the IP Catalog. Refer to Select and Instantiate the PHY IP Core on page 17 for more details.
Page 104 6. Create a transceiver reset controller. You can use your own reset controller or use the Intel Cyclone 10 GX Transceiver Native PHY Reset Controller IP. 7. Connect the Intel Cyclone 10 GX Transceiver Native PHY to the PLL IP and the reset controller.
Page 105 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Table 91. RX PMA Parameters Parameter Range Number of CDR reference clocks 1 to 5 Selected CDR reference clock 0 to 4 Selected CDR reference clock frequency 322.265625 MHz and 644.53125 MHz...
Page 106 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Table 95. Block Sync Parameters Parameter Range Enable RX block synchronizer Enable rx_enh_blk_lock port Table 96. Gearbox Parameters Parameter Range Enable TX data polarity inversion Enable RX data polarity inversion Table 97.
Page 107 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 2.6.2.4. Native PHY IP Ports for 10GBASE-R and 10GBASE-R with IEEE 1588v2 Transceiver Configurations Figure 49. High BER This figure shows the status signal going high when there are errors on the rx_enh_highber output.
Page 108: 2.5G/5G/10G Multi-Rate Ethernet Phy Intel Fpga Ip Core
• Low Latency Ethernet 10G MAC Intel FPGA IP User Guide Describes the Low Latency Ethernet 10G MAC Intel FPGA IP core. • Low Latency Ethernet 10G MAC Intel Cyclone 10 GX FPGA IP Design Example User Guide ® ®...
Page 109 Final Intel verifies the IP core with final timing models for this device family. The IP core meets all functional and timing requirements for the device family. This IP core is ready to be used in production designs.
Page 110 (USXGMII) 2.6.3.2. Using the IP Core The Intel FPGA IP Library is installed as part of the Intel Quartus Prime Pro Edition installation process. You can select the 1G/2.5G/5G/10G Multi-rate Ethernet Intel FPGA IP core from the library and parameterize it using the IP parameter editor.
Page 111 353 2.6.3.3. Functional Description The 1G/2.5G/5G/10G Multi-rate PHY Intel FPGA IP core for Intel Cyclone 10 GX devices implements the 10M to 10Gbps Ethernet PHY in accordance with the IEEE 802.3 Ethernet Standard. This IP core handles the frame encapsulation and flow of data between a client logic and Ethernet network via a 10M to 10GbE PCS and PMA (PHY).
Page 112 • Transceiver PHY dynamic reconfiguration interface—an Avalon-MM interface to read and write the Intel Cyclone 10 GX Native PHY IP core registers. This interface supports dynamic reconfiguration of the transceiver. It is used to configure the transceiver operating modes to switch to desired Ethernet operating speeds.
Page 113 10G transceiver PLL. Therefore, the 312.5 MHz clock must derived from the transceiver 10G reference clock for 10M/100M/1G/2.5G/5G/10G (USXGMII) variant. The 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP core for Intel Cyclone 10 GX devices supports up to ±100 ppm clock frequency difference. 2.6.3.3.2. Timing Constraints Constrain the PHY based on the fastest speed.
Page 114 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Table 107. Types of Register Access Access Definition Read only. Read and write. Read, and write and clear. The user application writes 1 to the register bit(s) to invoke a defined instruction.
Page 115 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Addr Name Description Access HW Reset Value Bit [4]: Reserved — — Bit [5]: AUTO_NEGOTIATION_COMPLETE A value of 1 indicates the Auto-Negotiation process is completed. Bit [15:6]: Reserved —...
Page 116 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Addr Name Description Access HW Reset Value 0x412 Auto-Negotiation link timer. Sets the link timer value in [19:14 [19:14]: usxgmii_link_tim bit [19:14] from 0 to 2 ms in approximately 0.05 ms...
Page 117 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 2.6.3.5.1. Clock and Reset Signals Table 109. Clock and Reset Signals Signal Name Direction Width Description Clock signals Input Clock for the Avalon-MM control and status csr_clk interface. Intel recommends 125 – 156.25 MHz for this clock.
Page 118 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 2.6.3.5.2. Operating Mode and Speed Signals Table 110. Transceiver Mode and Operating Speed Signals Signal Name Direction Width Description Output Connect this signal to the MAC. This signal...
Page 119 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Signal Name Direction Width Description Speed Toggle Rate 2.5G Asserted once every 4 clock cycles Asserted once every 2 clock cycles Asserted in every clock cycle RX XGMII signals—synchronous to...
Page 120 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 2.6.3.5.4. Status Signals Table 112. Status Signals Signal Name Direction Clock Width Description Domain Output Synchronous Asserted when auto-negotiation is led_an completed. rx_clkout Output Synchronous Asserted when the link synchronization for rx_block_lock 10GbE is successful.
Page 121: Xaui Phy Ip Core
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Table 115. Avalon-MM Interface Signals Signal Name Direction Width Description Input Use this bus to specify the register address to read csr_address from or write to. The width is: •...
Page 122: Pci Express (Pipe)
Definition Media Access Control. Media independent interface. Open System Interconnection. Physical Coding Sublayer. Physical Layer in OSI 7-layer architecture, also in Intel device scope is: PCS + PMA. Physical Medium Attachment. Physical Medium Dependent. SGMII Serial Gigabit Media Independent Interface.
Page 123: Transceiver Channel Datapath For Pipe
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Related Information PHY Interface For the PCI Express, SATA, and USB 3.1 Architectures 2.7.1. Transceiver Channel Datapath for PIPE Figure 57. Transceiver Channel Datapath for PIPE Gen1/Gen2 Configurations...
Page 124 2'b00 on the input signal initiates a data rate switch from Gen2 to Gen1. 2.7.2.1.2. Transmitter Electrical Idle Generation The PIPE interface block in Cyclone 10 GX devices puts the transmitter buffer in an electrical idle state when the electrical idle input signal is asserted. During electrical idle, the transmitter buffer differential and common mode output voltage levels are compliant with the PCIe Base Specification 2.0 for both PCIe Gen1 and Gen2 data...
Page 125 PCIe specification. pipe_rx_status[2:0] 2.7.2.1.6. Receiver Detection The PIPE interface block in Cyclone 10 GX transceivers provides an input signal for the receiver detect operation. The PCIe pipe_tx_detectrx_loopback[0:0] protocol requires this signal to be high during the Detect state of the LTSSM. When the...
Page 126 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 • For INSERT/DELETE cases: The flag status appears on the COM symbol of the SKP ordered set where insertion or deletion occurs. • For FULL/EMPTY cases: The flag status appears where the character is inserted or deleted.
Page 127 The received data is also available to the FPGA fabric through the rx_parallel_data port. This loopback mode is based on PCIe specification 2.0. Cyclone 10 GX devices provide an input signal to enable this loopback pipe_tx_detectrx_loopback[0:0] mode.
Page 128: How To Connect Tx Plls For Pipe Gen1 And Gen2 Modes
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 2.7.3. How to Connect TX PLLs for PIPE Gen1 and Gen2 Modes Figure 63. Use fPLL for Gen1/Gen2 x1 Mode X1 Network Ch 5 fPLL1 ATX PLL1 Ch 4...
Page 129 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Figure 64. Use ATX PLL for Gen1/Gen2 x1 Mode X1 Network Ch 5 fPLL1 ATX PLL1 Ch 4 Master CGB1 Ch 3 Ch 2 fPLL0 Master Ch 1...
Page 130 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Figure 65. Use ATX PLL or fPLL for Gen1/Gen2 x4 Mode Network Network Ch 5 Ch 4 Connections Done via X1 Network fPLL1 Master CGB1 Ch 3 ATX PLL1...
Page 131: How To Implement Pci Express (Pipe) In Cyclone 10 Gx Transceivers
Parameters for Cyclone 10 GX Native PHY IP in PIPE Gen1, Gen2 Modes This section contains the recommended parameter values for this protocol. Refer to Using the Cyclone 10 GX Transceiver Native PHY IP Core for the full range of parameter values.
Page 132 Parameters for Cyclone 10 GX Native PHY IP in PIPE Gen1, Gen2 Modes - TX This section contains the recommended parameter values for this protocol. Refer to Using the Cyclone 10 GX Transceiver Native PHY IP Core for the full range of parameter values.
Page 133 Parameters for Cyclone 10 GX Native PHY IP in PIPE Gen1, Gen2 Modes - RX This section contains the recommended parameter values for this protocol. Refer to Using the Cyclone 10 GX Transceiver Native PHY IP Core for the full range of parameter values.
Page 134 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Parameter Gen1 PIPE Gen2 PIPE RX FIFO mode low_latency low_latency Optional Optional Enable port tx_std_pcfifo_full Enable port Optional Optional tx_std_pcfifo_empty Enable port Optional Optional rx_std_pcfifo_full Enable port Optional...
Page 135: Fpll Ip Parameter Core Settings For Pipe
Parameter Settings for Cyclone 10 GX fPLL IP core in PIPE Gen1, Gen2 modes This section contains the recommended parameter values for this protocol. Refer to Using the Cyclone 10 GX Transceiver Native PHY IP Core for the full range of parameter values.
Page 136 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Parameter Gen1 PIPE Gen2 PIPE Enable manual counter configuration Disable Disable Enable ATX to fPLL cascade clock input Disable Disable port Settings Bandwidth Low, Medium, High Low, Medium, High...
Page 137: Atx Pll Ip Parameter Core Settings For Pipe
Parameters for Cyclone 10 GX ATX PLL IP core in PIPE Gen1, Gen2 modes This section contains the recommended parameter values for this protocol. Refer to Using the Cyclone 10 GX Transceiver Native PHY IP Core for the full range of parameter values.
Page 138 Generate C Header file Generate MIF (Memory Initialize file) Generation Options Generate parameter documentation file Enable Enable Related Information Using the Cyclone 10 GX Transceiver Native PHY IP Core on page 26 ® ® Intel Cyclone 10 GX Transceiver PHY User Guide...
Page 139: Native Phy Ip Ports For Pipe
Table 126. Ports for Cyclone 10 GX Transceiver Native PHY in PIPE Mode This section contains the recommended settings for this protocol. Refer to Using the Cyclone 10 GX Transceiver Native PHY IP Core for the full range of parameter settings.
Page 140 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Port Direction Clock Domain Description The 500 MHz clock output provided to the pipe_hclk_out[0] PHY - MAC interface. PIPE Input from PHY - MAC Layer The TX parallel data driven from the MAC.
Page 141 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Port Direction Clock Domain Description When 1'b1, instructs the PHY layer to invert pipe_rx_polarity[(N-1): the polarity on the received data. Asynchronous Active High Requests the PHY to change its power state to the specified state.
Page 142 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Port Direction Clock Domain Description Signal from the Master clock generation buffer, indicating that the rate switch has completed. Use this signal for bonding mode pipe_sw_done[1:0] only (x2 and x4).
Page 143: Fpll Ports For Pipe
Table 127. Bit Mappings When the Simplified Interface Is Disabled This section contains the recommended settings for this protocol. Refer to Using the Cyclone 10 GX Transceiver Native PHY IP Core for the full range of parameter values. Signal Name...
Page 144 For Gen 2x2, x4 connect the output pcie_sw_done[1:0] from fPLL to the input of Native PHY . pipe_sw_done Related Information Using the Cyclone 10 GX Transceiver Native PHY IP Core on page 26 ® ® Intel Cyclone 10 GX Transceiver PHY User Guide...
Page 145: Atx Pll Ports For Pipe
2.7.10. ATX PLL Ports for PIPE Table 129. ATX PLL Ports for PIPE This section contains the recommended settings for this protocol. Refer to Using the Cyclone 10 GX Transceiver Native PHY IP Core for the full range of parameter settings. Port...
Page 146: How To Place Channels For Pipe Configurations
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 2.7.11. How to Place Channels for PIPE Configurations Instead of the fitter or software model, the hardware dictates all the placement restrictions. The restrictions are listed below: •...
Page 147 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 The following figures show the default configurations: Figure 67. x2 Configuration fPLL Master Transceiver bank fPLL Master fPLL Master Transceiver bank fPLL Master Master CH Data CH Physical...
Page 148 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Figure 68. x4 Configuration The figure below shows an alternate way of placing 4 bonded channels. In this case, the logical PCS Master Channel number 2 must be specified as Physical channel 4.
Page 149: Cpri
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 As indicated in the figures above, the fitter picks either physical CH1 or CH4 as the PCS master in bonded configurations for PIPE. 2.8. CPRI The common public radio interface (CPRI) is a high-speed serial interface developed for wireless network radio equipment controller (REC) to uplink and downlink data from available remote radio equipment (RE).
Page 150 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Table 131. Channel Width Options for Supported Serial Data Rates Channel Width (FPGA-PCS Fabric) Serial Data Rate 8/10 Bit Width 16/20 Bit Width (Mbps) 8-Bit 16-Bit 16-Bit 32-Bit (25) 614.4...
Page 151: Supported Features For Cpri
Lower delay uncertainty is always desired for increased spectrum efficiency and bandwidth. The Cyclone 10 GX devices are designed with features to minimize the delay uncertainty for both RECs and REs.
Page 152: Word Aligner In Manual Mode For Cpri
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Figure 72. Word Aligner in Deterministic Mode Waveform rx_clkout rx_std_wa_patternalign f1e4b6e4 b9dbf1db 915d061d e13f913f 7a4ae24a bbae9b10 bcbcbcbc 95cd3c50 91c295cd rx_parallel_data rx_errdetect 1101 0000 1010 1000 0010 1010 0000...
Page 153: How To Implement Cpri In Cyclone 10 Gx Transceivers
Related Information Word Aligner on page 305 2.8.4. How to Implement CPRI in Cyclone 10 GX Transceivers You should be familiar with the Standard PCS and PMA architecture, PLL architecture, and the reset controller before implementing your CPRI protocol. 1. Instantiate the Cyclone 10 Transceiver Native PHY IP from the IP Catalog.
Page 154 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Figure 74. Signals and Ports of Native PHY IP for CPRI Cyclone 10 Transceiver Native PHY reconfig_reset tx_cal_busy NIOS Reconfiguration reconfig_clk rx_cal_busy Hard Calibration IP Registers reconfig_avmm TX PMA...
Page 155: Native Phy Ip Parameter Settings For Cpri
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Figure 75. Connection Guidelines for a CPRI PHY Design tx_ready reset rx_ready Reset Controller pll_sel pll_locked pll_refclk PLL IP Core pll_cal_busy tx_serialclk0 rx_cdr_refclk tx_clkout Data Generator tx_serial_data tx_parallel_data...
Page 156 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Table 136. TX PMA Parameters Parameter Value TX channel bonding mode Not Bonded / PMA Bonding Only / PMA and PCS Bonding TX local clock division factor Number of TX PLL clock inputs per channel...
Page 157 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Parameters Value Enable tx_std_pcfifo_full port Enable tx_std_pcfifo_empty port Enable rx_std_pcfifo_full port Enable rx_std_pcfifo_empty port TX byte serializer mode Serialize x2 RX byte deserializer mode Deserialize x2 Enable TX 8B/10B encoder...
Page 158: Other Protocols
2.9. Other Protocols 2.9.1. Using the "Basic (Enhanced PCS)" Configuration You can use Cyclone 10 GX transceivers to configure the Enhanced PCS to support other 10G or 10G-like protocols. The Basic (Enhanced PCS) transceiver configuration rule allows access to the Enhanced PCS with full user control over the transceiver interfaces, parameters, and ports.
Page 159 You should be familiar with the Basic (Enhanced PCS) and PMA architecture, PLL architecture, and the reset controller before implementing the Basic (Enhanced PCS) Transceiver Configuration Rule. 1. Open the IP Catalog and select the Cyclone 10 GX Transceiver Native PHY IP. Refer to Select and Instantiate the PHY IP Core on page 17 for more details.
Page 160 2.9.1.2. Native PHY IP Parameter Settings for Basic (Enhanced PCS) This section contains the recommended parameter values for this protocol. Refer to Using the Cyclone 10 GX Transceiver Native PHY IP Core for the full range of parameter values. ®...
Page 161 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Table 141. General and Datapath Parameters The first two sections of the Parameter Editor for the Transceiver Native PHY provide a list of general and datapath options to customize the transceiver.
Page 162 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Parameter Range Enable rx_is_lockedtodata port On / Off Enable rx_is_lockedtoref port On / Off Enable rx_set_locktodata and rx_set_locktoref ports On / Off Enable rx_serialpbken port On / Off...
Page 163 Table 146. Generate Options Parameters Parameter Range Generate parameter documentation file On / Off Related Information Using the Cyclone 10 GX Transceiver Native PHY IP Core on page 26 ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 164 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 2.9.1.3. How to Enable Low Latency in Basic Enhanced PCS In the Parameter Editor, use the following settings to enable low latency: 1. Select the Enable 'Enhanced PCS' low latency mode option.
Page 165 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Figure 80. RX FIFO Basic Mode Operation rx_clkout (write side) rx_coreclkin (read side) rx_parallel_data[63:0] 64’ d 0 64’ d 1 64’ d 2 64’ d 3 64’ d 4 64’...
Page 166: Using The Basic/Custom, Basic/Custom With Rate Match Configurations Of Standard Pcs
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 2.9.1.6. TX Data Polarity Inversion Use the TX data polarity inversion feature to swap the positive and negative signals of a serial differential link if they were erroneously swapped during board layout. To enable TX data polarity inversion, select the Enable TX data polarity inversion option in the Gearbox section of Platform Designer.
Page 167 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Figure 83. Transceiver Channel Datapath and Clocking for the Basic and Basic with Rate Match Configurations The clocking calculations in this figure are for an example when the data rate is 1250 Mbps and the PMA width is 10 bits.
Page 168 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Figure 84. Transceiver Channel Datapath and Clocking for Basic Configuration with Low Latency Enabled The clocking calculations in this figure are for an example when the data rate is 1250 Mbps and the PMA width is 10 bits.
Page 169 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Note: • is asserted whenever there is a pattern match. rx_patterndetect • is asserted after the word aligner achieves synchronization. rx_syncstatus • is asserted to re-align and resynchronize.
Page 170 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Figure 86. Manual Mode when the PCS-PMA Interface Width is 10 Bits = 10'h3BC and the word aligner pattern = 10'h3BC tx_parallel_data rx_std_wa_patternalign tx_parallel_data rx_parallel_data rx_patterndetect rx_syncstatus rx_std_wa_patternalign...
Page 171 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 The 8B/10B encoder and decoder add the following additional ports: • tx_datak • rx_datak • rx_errdetect • rx_disperr • rx_runningdisp 1. Set the RX word aligner mode to synchronous state machine.
Page 172 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 The RX bit slip feature is optional and may or may not be enabled. Figure 90. RX Bit Slip in 8-bit Mode = 8'hbc tx_parallel_data rx_std_bitslipboundarysel 01111 rx_bitslip...
Page 173 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Figure 94. RX Polarity Inversion rx_polinv tx_parallel_data 11111100001110111100 rx_parallel_data 11111100001... 00000011110001000011 11111100001110111100 rx_patterndetect rx_syncstatus 2.9.2.5. RX Bit Reversal The RX bit reversal feature can be enabled in low latency, basic, and basic rate match mode.
Page 174 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 1. Select basic (single width) in the RX rate match FIFO mode list. 2. Enter values for the following parameters. Parameter Value Description RX rate match insert/delete +ve...
Page 175 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 The following figure shows the deletion of D5 when the upstream transmitter reference clock frequency is greater than the local receiver reference clock frequency. It asserts for one parallel clock cycle while the rx_std_rmfifo_full deletion takes place.
Page 176 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 The rate match FIFO can insert as many pairs of skip patterns into a cluster necessary to avoid the rate match FIFO from under running. The 10-bit skip pattern can appear on the MSByte, the LSByte, or both, of the 20-bit word.
Page 177 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Figure 104. Rate Match FIFO Becoming Empty After Reading out the 20-Bit Word D5D6 tx_parallel_data[19:0] tx_parallel_data[9:0] rx_parallel_data[19:10] /K30.7/ rx_parallel_data[9:0] /K30.7/ rx_std_rmfifo_empty 2.9.2.9. 8B/10B Encoder and Decoder To enable the 8B/10B Encoder and the 8B/10B Decoder, select the Enable TX 8B/10B Encoder and Enable RX 8B/10B Decoder options on the Standard PCS tab in the IP Editor.
Page 178 RD– dataout[9:0] 2.9.2.11. How to Enable Low Latency in Basic In the Cyclone 10 GX Transceiver Native PHY IP Parameter Editor, use the following settings to enable low latency: 1. Select the Enable 'Standard PCS' low latency mode option. 2. Select either low_latency or register FIFO in the TX FIFO mode list.
Page 179 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Note: values in the following figures are based on the TX and RX rx_parallel_data bit reversal features being disabled. Figure 106. TX Bit Slip in 8-bit Mode = 8'hbc.
Page 180 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 2.9.2.14. TX Bit Reversal The TX bit reversal feature can be enabled in low latency, basic, and basic rate match mode. The word aligner is available in any mode. This feature is parameter-based, and creates no additional ports.
Page 181 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Figure 112. Signals and Ports of Native PHY IP for Basic, Basic with Rate Match Configurations Cyclone 10 Transceiver Native PHY reconfig_reset Reconfiguration Nios Hard tx_cal_busy reconfig_clk Registers...
Page 182 2.9.2.17. Native PHY IP Parameter Settings for Basic, Basic with Rate Match Configurations This section contains the recommended parameter values for this protocol. Refer to Using the Cyclone 10 GX Transceiver Native PHY IP Core for the full range of parameter values. Table 147.
Page 183 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Table 149. RX PMA Parameters Parameter Range Number of CDR reference clocks 1, 2, 3, 4, 5 Selected CDR reference clock 0, 1, 2, 3, 4 Selected CDR reference clock frequency...
Page 184 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Parameter Range Enable TX 8B/10B disparity control On/Off Enable RX 8B/10B decoder On/Off Disabled RX rate match FIFO mode Basic 10-bit PMA (for Basic with Rate Match) Basic 20-bit PMA (for Basic with Rate Match)
Page 185: How To Implement Pcs Direct Transceiver Configuration Rule
PCS Direct Transceiver Configuration Rule. 1. Open the IP Catalog and select Cyclone 10 GX Transceiver Native PHY IP. 2. Select PCS Direct from the Transceiver configuration rules list located under Datapath Options.
Page 186: Simulating The Transceiver Native Phy Ip Core
Use simulation to verify the Native PHY transceiver functionality. The Quartus Prime software supports register transfer level (RTL) and gate-level simulation in both ® ModelSim - Intel FPGA Edition and third-party simulators. You run simulations using your Quartus Prime project files. ® ®...
Page 187: Nativelink Simulation Flow
NativeLink—This flow simplifies simulation by allowing you to start a simulation from the Quartus Prime software. This flow automatically creates a simulation script and compiles design files, IP simulation model files, and Intel simulation library models. Note: The Quartus Prime Pro Edition software does not support NativeLink RTL simulation •...
Page 188 5. In the Tool name list, select your simulator. Note: ModelSim refers to ModelSim SE and PE. These simulators use the same commands as QuestaSim.ModelSim - Intel FPGA Edition refers to ModelSim - Intel FPGA Edition Starter Edition and ModelSim - Intel FPGA Edition Subscription Edition.
Page 189 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 2.10.1.2. How to Use NativeLink to Run a ModelSim RTL Simulation Figure 115. NativeLink Simulation Flow Diagram Specify EDA Simulator & Simulator Directory Run RTL Functional or Gate-Level Simulation...
Page 190 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Complete the following steps to run an RTL functional simulation: 1. Open your Quartus Prime project. 2. On the Tools menu, select Run Simulation Tool, then select RTL Simulation or Gate Level Simulation.
Page 191 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Figure 116. Using NativeLink with Third-Party Simulators Specify EDA Simulator & Simulator Directory Perform Functional Simulation Does Does Simulation Give Simulation Give Expected Results? Expected Results? Debug Design &...
Page 192: Scripting Ip Simulation
.spd files necessary for the ip-setup-simulation utility. The Intel Quartus Prime software provides utilities to help you generate and update IP simulation scripts. You can use the ip-setup-simulation utility to generate a combined simulator setup script, for all Intel FPGA IP in your design, for each supported simulator.
Page 193: Custom Simulation Flow
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 2.10.3. Custom Simulation Flow The custom simulation flow allows you to customize the simulation process for more complex simulation requirements. This flow allows you to control the following aspects of your design: •...
Page 194 2. Implementing Protocols in Intel Cyclone 10 GX Transceivers UG-20070 | 2018.09.24 Figure 117. Custom flow Simulation Compile Sim Model Libs Using Sim Lib Compiler Start Simulator & Open Quartus Prime Project Compile Design, Testbench, & Simulation Libraries Load Design &...
Page 195 UG-20070 | 2018.09.24 Note: Because the ModelSim - Intel FPGA Edition software provides precompiled simulation libraries, you do not have to compile simulation libraries if you are using the software. Complete the following steps to compile the simulation model libraries using the Simulation Library Compiler: 1.
Page 196: Implementing Protocols In Intel Cyclone 10 Gx Transceivers Revision History
Document Changes Version 2018.09.24 Made the following changes to the "Using the Cyclone 10 GX Transceiver Native PHY IP Core" section: • Added details about how to enable the transceiver toolkit capability in the "Dynamic Reconfiguration Parameters" section. Made the following changes to the "1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP Core"...
Page 197 OBSAI RP3 v4.1" protocols in the "Transceiver Protocols and PHY IP Support" section. • Added a note that Intel Cyclone 10 GX is only supported with Intel Quartus Prime Pro Edition 17.1 and future versions in the "Transceiver Design IP Blocks" section.
Page 198: Plls And Clock Networks
Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 199 3. PLLs and Clock Networks UG-20070 | 2018.09.24 Figure 118. Cyclone 10 GX PLLs and Clock Networks Transceiver x1 Clock Lines x6 Clock Lines xN Clock Lines Bank fPLL Local CGB Master Local CGB fPLL CDR/CMU Local CGB Master Local CGB...
Page 200: Plls
3. PLLs and Clock Networks UG-20070 | 2018.09.24 3.1. PLLs Table 155. Transmit PLLs in Cyclone 10 GX Devices PLL Type Characteristics Advanced Transmit (ATX) PLL • Best jitter performance • LC tank based voltage controlled oscillator (VCO) • Used for both bonded and non-bonded channel...
Page 201: Atx Pll
The input reference clock to the dedicated reference clock pin is a differential signal. Intel recommends using the dedicated reference clock pin as the input reference clock source for the best jitter performance. The input reference clock must be stable and free-running at device power-up for proper PLL operation and PLL calibration.
Page 202 Configuration Profiles section, multiple reconfiguration profiles can be enabled. This allows to create, store, and analyze the parameter settings for multiple configurations or profiles of the ATX PLL IP. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 203: Fpll
N Counter Pump and M Counter Output of Another fPLL with PLL Cascading Loop Filter Down Global Clock or Core Clock Delta Sigma fbclk Modulator C Counter ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 204 • Global clock or the core clock network The input reference clock is a differential signal. Intel recommends using the dedicated reference clock pin as the input reference clock source for best jitter performance. For protocol jitter compliance at datarate > 10 Gbps, Intel recommends using the dedicated reference clock pin in the same triplet with the fPLL as the input reference clock source.
Page 205 The C counters can be configured to select any VCO phase and a delay of up to 128 clock cycles. The selected VCO phase can be changed dynamically. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 206: Cmu Pll
The input reference clock is a differential signal. For protocol jitter compliance at a datarate > 10 Gbps, Intel recommends using the dedicated reference clock pin in the same triplet with the CMU PLL as the input reference clock source.
Page 207 There is a pre-divider to lower the frequency in case the frequency is too high. Related Information • Calibration on page 373 • Cyclone 10 GX Device Datasheet ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 208: Input Reference Clock Sources
(2) Dedicated refclk pin can be used as an input reference clock source only for ATX or fPLL or to the reference clock network. Reference clock network can then drive the CMU PLL. (3) The output of another PLL can be used as an input reference clock source during PLL cascading. Cyclone 10 GX transceivers support fPLL to fPLL cascading. Note:...
Page 209: Dedicated Reference Clock Pins
3.2.2. Receiver Input Pins Receiver input pins can be used as an input reference clock source to transceiver PLLs. However, they cannot be used to drive core fabric. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 210: Pll Cascading As An Input Reference Clock Source
PLL cascading can generate frequency outputs not normally possible with a single PLL solution. In PLL cascading, PLL outputs are connected to the feedback and cascading clock network. The transceiver in Cyclone 10 GX devices support fPLL to fPLL cascading, with only maximum two fPLLs allowed in the cascading chain.
Page 211: X1 Clock Lines
The x1 clock lines can be driven by the ATX PLL, fPLL, or by either one of the two channel PLLs (channel 1 and 4 when used as a CMU PLL) within a transceiver bank. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 212: X6 Clock Lines
There are two x6 clock lines per transceiver bank, one for each master CGB. Any channel within a transceiver bank can be driven by the x6 clock lines. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 213 Figure 125. x6 Clock Lines Network Ch 5 Bottom Ch 4 CMU or CDR Master Ch 3 Ch 2 Ch 1 CMU or CDR Master Ch 0 ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 214: Xn Clock Lines
CGB is used, and the local CGB within each channel is bypassed. For non-bonded configurations, the master CGB provides a high speed serial clock output to each channel. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 215 Ch 0 xN Up xN Down Related Information • Implementing x6/xN Bonding Mode on page 236 • x6/xN Bonding on page 222 • Cyclone 10 GX Data Sheet. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 216: Clock Generation Block
3. PLLs and Clock Networks UG-20070 | 2018.09.24 3.4. Clock Generation Block In Cyclone 10 GX devices, there are two types of clock generation blocks (CGBs) • Local clock generation block (local CGB) • Master clock generation block (master CGB) Each transmitter channel has a local clock generation block (CGB).
Page 217: Fpga Fabric-Transceiver Interface Clocking
The FPGA fabric-transceiver interface consists of clock signals from the FPGA fabric into the transceiver and clock signals from the transceiver into the FPGA fabric. These clock signals use the global (GCLK), regional (RCLK), and periphery (PCLK) clock ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 218 Parallel and Serial Clocks Serial Clock tx_clkout (from CGB) tx_pma_div_clkout Deserializer CDR Recovered Clock rx_clkout rx_pma_div_clkout The divided versions of the are available as tx_clkout rx_clkout , respectively. tx_pma_div_clkout rx_pma_div_clkout ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 219: Transmitter Data Path Interface Clocking
FPGA fabric is used to clock the write side tx_clkout of the phase compensation FIFO, then both sides of the FIFO have 0 ppm frequency difference because it is the same clock that is used. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 220: Receiver Data Path Interface Clocking
For configurations that use the byte deserializer block, the clock divided by 2 or 4 is used by the byte deserializer and the write side of the RX phase compensation FIFO. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 221: Unused/Idle Clock Line Requirements
Clock lines affected are unused idle receiver (RX) serial clock lines. Active RX serial clock lines and non-transceiver circuits are not impacted by this issue. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 222: Channel Bonding
For more information about unused or idle transceiver clock lines in the design. It describes the unused or idle transceiver clock lines assignments in the qsf file. 3.9. Channel Bonding For Cyclone 10 GX devices, two types of bonding modes are available: • PMA bonding •...
Page 223 Clock Lines on page 214 • Cyclone 10 GX Device Datasheet 3.9.1.2. PLL Feedback Compensation Bonding In PLL feedback compensation bonding, channels are divided into bonded groups based on physical location with a four-channel or six-channel transceiver bank. All channels within the same six-channel transceiver bank are assigned to the same bonded group.
Page 224: Pma And Pcs Bonding
For PMA bonding, either x6/xN or PLL feedback compensation bonding is used. For PCS bonding, some of the PCS control signals within the bonded group are skew aligned using dedicated hardware inside the PCS. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 225: Selecting Channel Bonding Schemes
Swapping of channels, when doing pin assignments, leads to errors. 3.9.3. Selecting Channel Bonding Schemes In Cyclone 10 GX devices, select PMA and PCS bonding for bonded protocols that are explicitly supported by the hard PCS blocks. For example, PCI-Express and SFI-S. ®...
Page 226: Skew Calculations
3.10. PLL Feedback and Cascading Clock Network The PLL feedback and cascading clock network spans the entire side of the device, and is used for PLL feedback compensation bonding and PLL cascading. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 227 Connection (2) fbclk ATX PLL 0 refclk fbclk Master CGB0 Bidirectional Tristate Buffer Legend refclk Lines PLL Cascading fbclk Lines PLL Feedback Compensation Bonding C, M, and CGB Outputs ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 228 For PLL cascading, connections (1) and (3) are used to connect the output of one PLL to the reference clock input of another PLL. The transceivers in Cyclone 10 GX devices support fPLL to fPLL. Only a maximum of two PLLs are allowed in the cascading chain.
Page 229 C Counters fPLL M Counter Phase Multiplexer Figure 136. Integer and Phase Aligned refclk N Counter L Counter C Counters Phase fPLL M Counter Multiplexer PLL Feedback Clock Network ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 230 Master CGB 1 Note: (1) RX pin used as reference clock Related Information • User Recalibration on page 383 • Implementing PLL Cascading on page 240 ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 231: Using Plls And Clock Networks
UG-20070 | 2018.09.24 3.11. Using PLLs and Clock Networks In Cyclone 10 GX devices, PLLs are not integrated in the Native PHY IP core. You must instantiate the PLL IP cores separately. Unlike in previous device families, PLL merging is no longer performed by the Quartus Prime software. This gives you more control, transparency, and flexibility in the design process.
Page 232 TX Channel fPLL TX Channel TX Channel TX Channel TX Channel Legend: TX channels placed in the same transceiver bank. TX channels placed in the adjacent transceiver bank. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 233 PLL instance. 3.11.1.3. Implementing Multi-Channel xN Non-Bonded Configuration Using the xN non-bonded configuration reduces the number of PLL resources and the reference clock sources used. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 234 Set the number of channels as per your design requirement. In this example, the number of channels is set to 10. 4. Create a top level wrapper to connect the PLL IP core to the Native PHY IP core. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 235: Bonded Configurations
In bonded configurations, the transceiver clock skew between the channels is minimized. Use bonded configurations for channel bonding to implement protocols such as PCIe and XAUI. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 236 Set the number of channels required by your design. In this example, the number of channels is set to 10. 4. Create a top level wrapper to connect the PLL IP core to Native PHY IP core. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 237 3.11.2.2. Implementing PLL Feedback Compensation Bonding Mode In this bonding mode, the channel span limitations of xN bonding mode are removed. This is achieved by dividing all channels into multiple bonding groups. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 238 CMU PLL cannot drive the master CGB, only the ATX PLL or fPLL can be used for feedback compensation bonding. 2. Configure the PLL IP core using the IP Parameter Editor. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 239 For fPLL, Read-Modify-Write 0x1 to offset address 0x126[0] of the fPLL. 2. Recalibrate the PLL. 3. After recalibration completes, ensure the PLL achieves lock. Dynamic reconfigure the PLL to change the feedback to master CGB. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 240: Implementing Pll Cascading
PLL. The second PLL generates the clock frequency required for the desired data rate. The transceivers in Cyclone 10 GX devices support fPLL to fPLL cascading. Only maximum two PLLs are allowed in the cascading chain.
Page 241: Timing Closure Recommendations
383 3.11.4. Timing Closure Recommendations Register mode is harder to close timing in Cyclone 10 GX devices. Intel recommends using negative edge capture on the RX side for periphery to core transfers greater than 240 MHz. To be specific, capture on a negative edge clock in the core and then immediately transfer to a positive edge clock.
Page 242 Requirements" section. • Added a sentence in fPLL/CMU PLL "For protocol jitter compliance at datarate > 10 Gbps, Intel recommends using the dedicated reference clock pin in the same triplet with the fPLL/CMU PLL as the input reference clock source."...
Page 243: Resetting Transceiver Channels
Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 244: Transceiver Phy Implementation
(feeding it to the core), you must instantiate altera_a10_xcvr_clock_module altera_a10_xcvr_clock_module reset_clock (.clk_in(mgmt_clk)); For more information about the CLKUSR pin, refer to the Cyclone 10 GX Pin Connection Guidelines. (29) There is only one centralized TRS instantiated for one or more Native PHY.
Page 245: How Do I Reset
You reset a transceiver PHY or PLL by integrating a reset controller in your system design to initialize the PCS and PMA blocks. You can save time by using the Intel- provided Transceiver PHY Reset Controller IP core, or you can implement your own reset controller that follows the recommended reset sequence.
Page 246 4.3.1.1. Recommended Reset Sequence How to Enable Model 1 Choose the Intel Cyclone 10 GX Default Settings for the Transceiver PHY Reset Controller IP. This populates the reset duration fields with the correct values required by the transceiver reset sequencer (TRS).
Page 247 The following steps detail the transmitter reset sequence during device operation. The step numbers correspond to the numbers in the following figure. 1. Perform the following steps: ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 248 = 70 μs Note: (1) The Cyclone 10 GX Default setting presets tx_digitalreset to 70 μs. (2) Area in gray is don’t care logic state. Related Information Cyclone 10 GX Device Datasheet 4.3.1.1.2. Resetting the Receiver During Device Operation Follow this reset sequence to reset the analog or digital blocks of the receiver at any point during the device operation.
Page 249 Use the following control settings to set the CDR lock mode: Table 157. Control Settings for the CDR in Manual Lock Mode rx_set_locktoref rx_set_locktodata CDR Lock Mode Automatic Manual-RX CDR LTR Manual-RX CDR LTD ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 250 This indicates rx_digitalreset that the receiver is now ready to receive data with the CDR in manual mode. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 251 (minimum of 70 μs) duration after is deasserted. tx_analogreset 5. Deassert after deasserting rx_analogreset tx_analogreset 6. Ensure is asserted for t (minimum of 4 μs) before rx_is_lockedtodata deasserting rx_digitalreset ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 252 5. Deassert after goes high. The tx_digitalreset pll_locked signal must stay asserted for a minimum tx_digitalreset tx_digitalreset duration after is deasserted. tx_analogreset ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 253 = 70 μs Note: (1) The Cyclone 10 GX Default setting presets ttx_digitalreset to 70 μs. (2) Area in gray is don’t care zone. RX Channel The numbers in this list correspond to the numbers in the following figure.
Page 254: Model 2: Acknowledgment Model
Enable the port in the TX PMA tx_analog_reset_ack Figure 155. Enabling the tx_analog_reset_ack Port • Enable the port in the RX PMA rx_analog_reset_ack Figure 156. Enabling the rx_analog_reset_ack Port ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 255 Figure 157. Transmitter Reset Sequence During Device Operation Device Power Up pll_cal_busy tx_cal_busy tx_analogreset tx_analogreset_ack pll_powerdown pll_locked tx_digitalreset tx_digitalreset Note: (1) Area in gray is don’t care logic state. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 256 2. Wait for to go high, to ensure successful assertion of tx_analogreset_ack goes high when TRS has successfully tx_analogreset tx_analogreset_ack completed the reset request for assertion. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 257 4.3.2.1.4. Dynamic Reconfiguration of Receiver Channel Using the Acknowledgment Model The numbers in this list correspond to the numbers in the following figure. 1. Assert while is low. rx_analogreset rx_digitalreset rx_cal_busy ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 258: Transceiver Blocks Affected By Reset And Powerdown Signals
Transceiver Blocks Affected by Specified Reset and Powerdown Signals Transceiver pll_powerdown tx_analogreset tx_digitalreset rx_analogreset rx_digitalreset Block CMU PLL ATX PLL fPLL Receiver Standard PCS Receiver Enhanced PCS continued... ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 259: Using The Transceiver Phy Reset Controller
The following figure illustrates the typical use of the Transceiver PHY Reset Controller in a design that includes a transceiver PHY instance and the transmit PLL. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 260 Figure 161. Transceiver PHY Reset Controller System Diagram Status Signals tx_ready rx_ready tx_analogreset Transceiver PHY Instance tx_digitalreset Reset Controller rx_analogreset Transmitter Transmitter clock rx_digitalreset (user-coded or Intel IP) reset rx_cal_busy Receiver Receiver rx_is_lockedtoref rx_is_lockedtodata tx_analogreset_ack rx_analogreset_ack pll_tx_cal_busy tx_cal_busy (1) pll_cal_busy (1) Transmit Transceiver Reset Sequencer Inferred Block...
Page 261: Parameterizing The Transceiver Phy Reset Controller Ip
When Off, the reset input is not synchronized. Use fast reset for simulation On /Off When On, the Transceiver PHY Reset Controller uses reduced reset counters for simulation. continued... ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 262 The value is rounded up to the nearest clock cycle. Note: Model 1 requires this to be set to 70 µs. Select the Cyclone 10 GX Default Settings preset. tx_digitalreset duration Specifies the time in ns to continue to assert the...
Page 263 The default value is 40 ns. Note: Model 1 requires this to be set to 70 µs. Select the Cyclone 10 GX Default Settings preset. rx_digitalreset duration Specifies the time in ns to continue to assert the...
Page 264: Transceiver Phy Reset Controller Interfaces
IP. The signal goes low when calibration is completed. This signal gates the TX reset sequence. The width of this signals depends on the number of TX channels. continued... ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 265 PLL has not reached the initial lock ( pll_locked deasserted) • is deasserted and pll_locked tx_manual deasserted When all of these conditions are false, the reset counter begins its countdown for deassertion of tx_digitalreset continued... ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 266 RX channels. Output Synchronous to the Asserted to power down a transceiver PLL circuit. When pll_powerdown[<p>-1:0 Transceiver PHY Reset asserted, the selected TX PLL is reset. Controller input clock. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 267: Transceiver Phy Reset Controller Resource Utilization
Checks the PLL status (for example, checks the status of pll_locked pll_cal_busy Note: You must ensure a stable reference clock is present at the PLL transmitter before releasing pll_powerdown ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 268: User-Coded Reset Controller Signals
A high on this signal indicates that the RX CDR is in the lock-to-reference rx_is_lockedtoref (LTR) mode. This signal may toggle or be deasserted when the CDR is in LTD mode. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 269: Combining Status Or Pll Lock Signals
PMA Bonding or for RX PCS channels. Note: If the design is not able to meet the maximum skew tolerance requirement with a positive margin, Intel recommends reassigning the channels’ locations that are not adjacent to the PCIe Hard IP block. ®...
Page 270 <IP_INSTANCE_NAME>—substitute the name of your reset controller IP instance or PHY IP instance • <½ coreclk period in ps>—substitute half of the clock period of your design in picoseconds ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 271: Resetting Transceiver Channels Revision History
Made the following changes: • Added a note "If the design is not able to meet the maximum skew tolerance requirement with a positive margin, Intel recommends reassigning the channels locations that are not adjacent to the PCIe Hard IP block." 2017.05.08 Initial release.
Page 272: Cyclone 10 Gx Transceiver Phy Architecture
Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 273 5. Cyclone 10 GX Transceiver PHY Architecture UG-20070 | 2018.09.24 Figure 168. Serializer Block The serializer block sends out the least significant bit (LSB) of the input data first. Serial Parallel Data Serializer Data Serial Parallel Clock Clock 5.1.1.2. Transmitter Buffer The transmitter buffer includes the following circuitry: •...
Page 274 R1* - Half of the actual on-chip termination selected. 5.1.1.2.1. High Speed Differential I/O To improve performance, the Cyclone 10 GX transmitter uses a new architecture in the output buffer—High Speed Differential I/O. You should select "High Speed Differential I/O" for I/O standard of Cyclone 10 GX transmitter pin in Quartus Prime Assignment Editor or QSF file.
Page 275: Receiver
5.1.1.2.4. Power Distribution Network (PDN) induced Inter-Symbol Interference (ISI) compensation The Cyclone 10 GX Transmitter driver includes a compensation circuitry to reduce PDN induced ISI jitter. You can enable this compensation circuitry to reduce jitter through QSF setting, Quartus Assignment Editor or Avalon-MM interface. The power consumption will increase when you enable the compensation.
Page 276 5. Cyclone 10 GX Transceiver PHY Architecture UG-20070 | 2018.09.24 Figure 171. Receiver PMA Block Diagram Receiver PMA Serial Serial Parallel Parallel Data Receiver Serial Data Receiver Data Data to FPGA Core Receiver Differential Input Deserializer Buffer Data Serial Clock Parallel Clock 5.1.2.1.
Page 277 Refer to Figure 173 on page 278. Cyclone 10 GX transceivers support high gain mode CTLE. High Gain Mode This mode provides both AC and DC gain. There are two bandwidth settings available for this mode.
Page 278 Frequency 5.1.2.1.5. Variable Gain Amplifier (VGA) Cyclone 10 GX channels have a variable gain amplifier to optimize the signal amplitude prior to the CDR sampling. VGA can only be operated in manual mode. VGA gain can be selected through Quartus Assignment Editor or Quartus Setting File (qsf) or the Avalon MM register.
Page 279 The values are written dynamically and do not require design re- compilation. Refer to Intel Cyclone 10 GX Register Map for details on the specific registers that set the CTLE gain values. Note: You must set VGA manually for all combinations of CTLE mode.
Page 280 5. Cyclone 10 GX Transceiver PHY Architecture UG-20070 | 2018.09.24 Related Information • Analog Parameter Settings on page 388 • Intel Cyclone 10 GX Register Map 5.1.2.2. Clock Data Recovery (CDR) Unit The PMA of each channel includes a channel PLL that you can configure as a receiver clock data recovery (CDR) for the receiver.
Page 281 5. Cyclone 10 GX Transceiver PHY Architecture UG-20070 | 2018.09.24 the CDR sees valid data; therefore, you should hold receiver PCS logic in reset ) for a minimum of 4 µs after remains rx_digitalreset rx_is_lockedtodata continuously asserted. 5.1.2.2.3. CDR Lock Modes You can configure the CDR in either automatic lock mode or manual lock mode.
Page 282: Loopback
5. Cyclone 10 GX Transceiver PHY Architecture UG-20070 | 2018.09.24 Figure 176. Deserializer Block Diagram The deserializer block sends out the LSB of the input data first. Serial Data Parallel Deserializer Data Parallel Serial Clock Clock 5.1.3. Loopback The PMA supports serial, diagnostic, and reverse loopback paths.
Page 283: Cyclone 10 Gx Enhanced Pcs Architecture
5. Cyclone 10 GX Transceiver PHY Architecture UG-20070 | 2018.09.24 Figure 178. Reverse Serial Loopback Path/Pre CDR Transmitter PMA Serial Parallel Data Parallel Transmitter Serial Data from FPGA Core Transmitter Data Transmitter Differential Output Serializer Buffer Data Parallel Clock Clock...
Page 284: Transmitter Datapath
Parallel and Serial Clocks Parallel and Serial Clocks Input Reference Clock Related Information Implementing Protocols in Intel Cyclone 10 GX Transceivers on page 16 5.2.1. Transmitter Datapath 5.2.1.1. Enhanced PCS TX FIFO The Enhanced PCS TX FIFO provides an interface between the transmitter channel PCS and the FPGA fabric.
Page 285 FIFO output. Note: Intel recommends that you implement a soft FIFO in the FPGA fabric with a minimum of 32 words under the following conditions: • When the Enhanced PCS TX FIFO is set to register mode.
Page 286 5. Cyclone 10 GX Transceiver PHY Architecture UG-20070 | 2018.09.24 5.2.1.2. Interlaken Frame Generator The Interlaken frame generator block takes the data from the TX FIFO and encapsulates the payload and burst/idle control words from the FPGA fabric with the framing layer’s control words (synchronization word, scrambler state word, skip word,...
Page 287 5. Cyclone 10 GX Transceiver PHY Architecture UG-20070 | 2018.09.24 Figure 182. Interlaken CRC-32 Generator The Interlaken CRC-32 generator implements the Interlaken protocol. Interlaken Metaframes with Embedded CRC-32 From the Interlaken Frame Generator CRC-32 Code to Scrambler Generator Metaframe Payload...
Page 288 The PRBS generator in Cyclone 10 GX devices is a shared hardened block between the Standard and Enhanced datapaths through the PCS instead of being two unique instances: one for Standard PCS and one for the Enhanced PCS.
Page 289 TX and RX tests in the 10G Ethernet mode. You can use the Cyclone 10 GX Pseudo Random Pattern (PRP) generator in the scrambler to generate random data pattern and seed that the scrambler can use.
Page 290 5. Cyclone 10 GX Transceiver PHY Architecture UG-20070 | 2018.09.24 5.2.1.6. Scrambler The scrambler randomizes data to create transitions to DC-balance the signal and help CDR circuits. The scrambler uses a x +1 polynomial and supports both synchronous scrambling used for Interlaken and asynchronous (also called self- synchronized) scrambling used for the 10GBASE-R protocol.
Page 291: Receiver Datapath
5. Cyclone 10 GX Transceiver PHY Architecture UG-20070 | 2018.09.24 5.2.1.7. Interlaken Disparity Generator The Interlaken disparity generator block is in accordance with the Interlaken protocol specification and provides a DC-balanced data output. The Interlaken protocol solves the unbounded baseline wander, or DC imbalance, of the 64B/66B coding scheme used in 10Gb Ethernet by inverting the transmitted data.
Page 292 5. Cyclone 10 GX Transceiver PHY Architecture UG-20070 | 2018.09.24 RX bitslip is engaged when the RX block synchronizer or is enabled to rx_bitslip shift the word boundary. On the rising edge of the bitslip signal of the RX block...
Page 293 The PRBS checker in Cyclone 10 GX devices is a shared hardened block between the Standard and Enhanced datapaths. Hence, there is only one set of control signals and registers for this feature.
Page 294 5. Cyclone 10 GX Transceiver PHY Architecture UG-20070 | 2018.09.24 Table 168. Supported PRBS Patterns PRBS Pattern 10 bit PCS-PMA width 64 bit PCS-PMA width PRBS7: x PRBS9: x PRBS15: x PRBS23: x PRBS31: x Figure 189. PRBS9 Verify Serial Implementation...
Page 295 5. Cyclone 10 GX Transceiver PHY Architecture UG-20070 | 2018.09.24 Figure 190. PRP Verifier Error Counter error_count Descrambler Test Pattern Detect Pseudo Random Verifier Refer to the Reconfiguration Interface and Dynamic Reconfiguration chapter for configuration details. Related Information Reconfiguration Interface and Dynamic Reconfiguration on page 315 5.2.2.8.
Page 296 FIFO output. The RX FIFO in register mode has one register stage or one parallel clock latency. Note: Intel recommends that you implement a soft FIFO in the FPGA fabric with minimum of 32 words under the following conditions: •...
Page 297 5. Cyclone 10 GX Transceiver PHY Architecture UG-20070 | 2018.09.24 For example, after frame lock is achieved, data is written after the first alignment word (SYNC word) is found on that channel. As a result, (FIFO rx_enh_fifo_pempty partially empty flag ) of that channel goes low. You must monitor the flags of all channels.
Page 298 5. Cyclone 10 GX Transceiver PHY Architecture UG-20070 | 2018.09.24 Deletable Case Word Previous Current Output Upper Word If only one word is deleted, data shifting is necessary because the datapath is two words wide. After two words have been deleted, the FIFO stops writing for one cycle and a synchronous flag ( ) appears on the next block of 8-byte data.
Page 299: Cyclone 10 Gx Standard Pcs Architecture
5. Cyclone 10 GX Transceiver PHY Architecture UG-20070 | 2018.09.24 Case Word Input Output I-DS I-DS I-In I-In I-In Figure 194. IDLE Word Insertion This figure shows the insertion of IDLE words in the receiver data stream. Before Insertion rx_parallel_data[79:0]...
Page 300: Transmitter Datapath
5. Cyclone 10 GX Transceiver PHY Architecture UG-20070 | 2018.09.24 5.3.1. Transmitter Datapath 5.3.1.1. TX FIFO (Shared with Enhanced PCS and PCIe Gen2 PCS) The TX FIFO interfaces between the transmitter PCS and the FPGA fabric and ensures reliable transfer of data and status signals. It compensates for the phase difference between the FPGA fabric clock and (the low-speed parallel clock).
Page 301 16 5.3.1.2.1. Bonded Byte Serializer The bonded byte serializer is available in Cyclone 10 GX devices, and is used in applications such as PIPE, CPRI, and custom applications where multiple channels are grouped together. The bonded byte serializer is implemented by bonding all the control signals to prevent skew induction between channels during byte serialization.
Page 302 5. Cyclone 10 GX Transceiver PHY Architecture UG-20070 | 2018.09.24 5.3.1.2.4. Byte Serializer Serialize x4 Mode The serialize x4 mode is used in high-speed applications such as the PCIe Gen2 protocol mode, where the FPGA fabric cannot operate as fast as the TX PCS.
Page 303 5. Cyclone 10 GX Transceiver PHY Architecture UG-20070 | 2018.09.24 5.3.1.3.1. 8B/10B Encoder Control Code Encoding Figure 199. Control Code Encoding Diagram tx_clkout tx_parallel_data[15:0] 8378 BCBC 0F00 BF3C tx_datak[1:0] Code Group D3.4 D24.3 D28.5 K28.5 D15.0 D0.0 D31.5 D28.1 signal indicates whether the 8-bit data being sent at the tx_datak port should be a control word or a data word.
Page 304 5. Cyclone 10 GX Transceiver PHY Architecture UG-20070 | 2018.09.24 are two bits each. The LSB of tx_dispval tx_forcedisp tx_dispval corresponds to the LSByte of the input data and the MSB corresponds to the MSByte of the input data. 5.3.1.3.5. 8B/10B Encoder Bit Reversal Feature Figure 200.
Page 305: Receiver Datapath
5. Cyclone 10 GX Transceiver PHY Architecture UG-20070 | 2018.09.24 Related Information Cyclone 10 GX Enhanced PCS Architecture on page 283 5.3.1.6. TX Bit Slip The TX bit slip allows the word boundary to be controlled by . The TX bit slip feature is used in applications, such tx_std_bitslipboundarysel as CPRI, which has a data rate greater than 6 Gbps.
Page 306 5. Cyclone 10 GX Transceiver PHY Architecture UG-20070 | 2018.09.24 5.3.2.1.2. Word Aligner Manual Mode In manual alignment mode, the word aligner operation is controlled by . The word aligner operation is edge-sensitive or level- rx_std_wa_patternalign sensitive to , depending upon the PCS-PMA interface rx_std_wa_patternalign width selected.
Page 307 5. Cyclone 10 GX Transceiver PHY Architecture UG-20070 | 2018.09.24 The PCS performs pattern detection on the incoming data from the PMA. The PCS aligns the data, after it indicates to the PMA the number of serial bits to clock slip the boundary.
Page 308 5. Cyclone 10 GX Transceiver PHY Architecture UG-20070 | 2018.09.24 PCS-PMA Supported Word Supported rx_std_wa_patte rx_syncstatus rx_patterndetect Interface Aligner Modes Word Aligner behavior behavior behavior rnalign Width Pattern Lengths FPGA fabric- asserted BITSLIP signal toggles. Manual 7, 10 Word alignment is...
Page 309 5. Cyclone 10 GX Transceiver PHY Architecture UG-20070 | 2018.09.24 PCS-PMA Supported Word Supported rx_std_wa_patte rx_syncstatus rx_patterndetect Interface Aligner Modes Word Aligner behavior behavior behavior rnalign Width Pattern Lengths double width word aligner updates the word boundary, only when the...
Page 310 PIPE 0 ppm • PCIe Related Information • How to Implement GbE, GbE with IEEE 1588v2 in Intel Cyclone 10 GX Transceivers on page 93 For more information about implementing rate match FIFO in GigE mode. • PCI Express (PIPE) on page 122 For more information about implementing rate match FIFO in PCIe mode.
Page 311 5. Cyclone 10 GX Transceiver PHY Architecture UG-20070 | 2018.09.24 5.3.2.4. 8B/10B Decoder The general functionality for the 8B/10B decoder is to take a 10-bit encoded value as input and produce an 8-bit data value and a 1-bit control value as output. In configurations with the rate match FIFO enabled, the 8B/10B decoder receives data from the rate match FIFO.
Page 312 5. Cyclone 10 GX Transceiver PHY Architecture UG-20070 | 2018.09.24 5.3.2.4.1. 8B/10B Decoder Control Code Encoding Figure 204. 8B/10B Decoder in Control Code Group Detection When the PCS-PMA Interface Width is 10 Bits tx_clkout datain[9:0] D3.4 D24.3 D28.5 K28.5 D15.0 D0.0...
Page 313 5. Cyclone 10 GX Transceiver PHY Architecture UG-20070 | 2018.09.24 Figure 205. Byte Deserializer Block Diagram Datapath from the Byte 8B/10B Decoder, Datapath to the RX PCS FIFO Deserializer Rate Match FIFO, or Word Aligner Low speed parallel clock 5.3.2.6.1. Byte Deserializer Disabled Mode In disabled mode, the byte deserializer is bypassed.
Page 314: Intel Cyclone 10 Gx Transceiver Phy Architecture Revision History
Made the following changes: • Removed the QPI configuration from the "Transmitter Buffer" section. 2017.11.06 Made the following changes: • Added a link to the Intel Cyclone 10 GX Register Map in the "Configuration Methods" section. 2017.05.08 Initial release. ® ® Intel...
Page 315: Reconfiguration Interface And Dynamic Reconfiguration
Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 316: Interacting With The Reconfiguration Interface
6. Reconfiguration Interface and Dynamic Reconfiguration UG-20070 | 2018.09.24 Table 174. Cyclone 10 GX Dynamic Reconfiguration Feature Support Reconfiguration Features Channel Reconfiguration PMA analog features • • Pre-emphasis • Continuous Time Linear Equalizer (CTLE) TX PLL • TX local clock dividers •...
Page 317 6. Reconfiguration Interface and Dynamic Reconfiguration UG-20070 | 2018.09.24 Figure 207. Reconfiguration Interface in Cyclone 10 GX Transceiver IP Cores Native PHY IP Core Ch0: Avalon Reconfiguration Interface Avalon-MM Master Ch1: Avalon Reconfiguration Embedded Controller in FPGA Interface or Embedded Processor on PCB...
Page 318: Reading From The Reconfiguration Interface
When two or more features share the same reconfiguration address, one feature's data bits are interleaved with another feature's data bits. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 319: Configuration Files
346 6.3. Configuration Files The Cyclone 10 GX Transceiver Native PHY and Transmit PLL IP cores optionally allow you to save the parameters you specify for the IP instances as configuration files. The configuration file stores addresses and data values for that specific IP instance.
Page 320 2'h0 hssi_tx_pcs_pma_interface_tx_pma_data_sel • with a value of 1'h0 hssi_tx_pcs_pma_interface_prbs_gen_pat • with a value of 4'h4 hssi_tx_pcs_pma_interface_sq_wave_num Writing to bit 7 of address 0x008 changes the feature. hssi_tx_pcs_pma_interface_pldif_datawidth_mode ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 321: Multiple Reconfiguration Profiles
You can generate the base and modified configuration files in the same or different folders. If you use the same folder, each configuration name must be unique. Intel recommends following the flow described in the Steps to Perform Dynamic Reconfiguration section when performing dynamic reconfiguration of either the Native PHY IP core or transmit PLL IP core.
Page 322: Embedded Reconfiguration Streamer
For the ATX PLL IP, you can control the embedded streamer block through the reconfiguration interface. Control and status signals of the streamer block are memory mapped in the PLL’s soft control and status registers. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 323 Note: The soft control and status registers at x340 and x341 are enabled when you enable the embedded reconfiguration streamer in the Native PHY IP core. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 324 Related Information • Steps to Perform Dynamic Reconfiguration on page 328 • Analog Parameter Settings on page 388 ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 325: Arbitration
6. Reconfiguration Interface and Dynamic Reconfiguration UG-20070 | 2018.09.24 6.6. Arbitration Figure 211. Cyclone 10 GX ATX PLL with Embedded Streamer Cyclone 10 GX ATX PLL IP Cyclone 10 GX ATX PLL Internal Configuration To/From Configuration PreSICE Registers Avalon-MM Reconfiguration...
Page 326 6. Reconfiguration Interface and Dynamic Reconfiguration UG-20070 | 2018.09.24 In Cyclone 10 GX devices, there are two levels of arbitration: • Reconfiguration interface arbitration with the PreSICE calibration engine When you have control over the internal configuration bus, refer to the second level of arbitration: Arbitration between multiple masters within the Native PHY/PLL IPs.
Page 327: Recommendations For Dynamic Reconfiguration
For all other reconfiguration scenarios, do not hold the PLL in reset before and during reconfiguration. When reconfiguring across data rates or protocol modes, Intel recommends that you hold the channel transmitter (analog and digital) associated with the PLL in reset during reconfiguration and recalibration of the PLL.You can use the...
Page 328: Steps To Perform Dynamic Reconfiguration
PRBS, place the channels in analog reset. For details about placing the channel in analog reset, refer to "Model 1: Default Model" and "Model 2: Acknowledgment Model" in the Resetting Transceiver Channels chapter. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 329 11. Release the channel analog resets. For details about placing the channel in reset, refer to "Model 1: Default Model" and "Model 2: Acknowledgment Model" in the Resetting Transceiver Channels chapter. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 330: Direct Reconfiguration Flow
PLL. You can use this flow to change the PMA analog settings, enable/disable PRBS generator, and checker hard blocks of the transceiver channel. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 331: Native Phy Ip Or Pll Ip Core Guided Reconfiguration Flow
PLL IP cores to store the parameter settings (MIF configuration file) to memory. With the configuration content saved, you can read from the memory and write the content ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 332 Changing PMA Analog Parameters on page 338 • Steps to Perform Dynamic Reconfiguration on page 328 • Resetting Transceiver Channels on page 243 • Calibration on page 373 ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 333: Reconfiguration Flow For Special Cases
The following table shows the addresses and bits for transmitter PLL switching. The number of exposed bits varies according to the number of tx_serial_clk transmitter PLLs you specify. Use the Native PHY reconfiguration interface for this operation. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 334 4. Perform a read-modify-write to bits[7:0] of address 0x111 using the encoded 8-bit value. 5. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic Reconfiguration. Related Information Steps to Perform Dynamic Reconfiguration on page 328 ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 335: Switching Reference Clocks
0x117 (Lookup Register) [7:0] Represents logical . Lookup register pll_refclk4 refclk4 stores the mapping from logical x117[7:0] to the physical refclk. refclk4 ATX refclk selection MUX. 0x112 [7:0] ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 336 MUX_0. refclk3 0x11B (Lookup Register) [7:0] Represents logical . Lookup pll_refclk4 refclk4 MUX_0 register stores the mapping from logical x11B[4:0] to the physical refclk for MUX_0. refclk4 continued... ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 337 For the CDR, specify the parameter on the RX PMA tab during the Native PHY IP parameterization. For the CMU, specify the Number of PLL reference clocks under the PLL tab when parameterizing the CMU PLL. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 338: Changing Pma Analog Parameters
328 6.12. Changing PMA Analog Parameters You can use the reconfiguration interface on the Transceiver Native PHY IP core to change the value of PMA analog features. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 339 RMWs using direct reconfiguration flow. Table 183. PMA Analog Settings that are Channel or System Dependent PMA Analog Feature Fitter Report Name Cyclone 10 GX Transceiver Register Map Attribute Name vod_output_swing_ctrl vod_output_swing_ctrl Pre-emphasis pre_emp_sign_1st_post_tap...
Page 340 — Examples: Slew rate, Equalizer Bandwidth, Compensation Enable. Table 184. PMA Analog Settings that are Device Dependent PMA Analog Feature Fitter Report Name Cyclone 10 GX Transceiver Register Map Attribute Name Slew Rate (TX Buffer) Slew_rate_ctrl Slew_rate_ctrl Equalizer Bandwidth...
Page 341: Changing Vod, Pre-Emphasis Using Direct Reconfiguration Flow
1st post-tap, read and store the value of address 0x105. 3. Select a valid value for the feature according to the Cyclone 10 GX register map. For example, a valid setting for pre-emphasis 1st post-tap has a bit encoding of 5'b00001.
Page 342: Changing Ctle Settings In Manual Mode Using Direct Reconfiguration Flow
CTLE AC gain in high gain mode, read and store the value of address 0x167[5:1]. 3. Select a valid value for the feature according to the Cyclone 10 GX register map. For example, a valid setting for CTLE AC Gain has a bit encoding of 5’b00000.
Page 343: Enabling And Disabling Loopback Modes Using Direct Reconfiguration Flow
328 • Cyclone 10 GX PMA Architecture on page 272 6.12.3. Enabling and Disabling Loopback Modes Using Direct Reconfiguration Flow Cyclone 10 GX devices have three loopback modes: • Serial Loopback • Reverse Serial Loopback (Pre-CDR) • Reverse Serial Loopback (Post-CDR) The loopback mode can be dynamically reconfigured by accessing the register space.
Page 344 Table 188. Bit Values to Be Set Address Bit Values 0x137[7] 1’b1 0x13C[7] 1’b0 0x132[5:4] 2’b00 0x142[4] 1’b1 0x11D[0] 1’b1 Note: No specific order to access these registers. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 345 0x137[7] 1’b0 0x13C[7] 1’b0 0x132[5:4] 2’b00 0x142[4] 1’b0 0x11D[0] 1’b0 Note: No specific order to access these registers. Related Information Steps to Perform Dynamic Reconfiguration on page 328 ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 346: Ports And Parameters
Read enable signal. Signal is active high. reconfig_read reconfig_clk Input Address bus. The lower 10 bits specify address reconfig_address[log2<N>+9:0] reconfig_clk and the upper bits specify the channel. continued... ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 347 A one-bit signal for each channel that reconfig_waitrequest[N-1:0] reconfig_clk indicates the Avalon interface is busy. Keep the Avalon command asserted until the interface is ready to proceed with the read/ continued... ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 348 Available in Native PHY and TX PLL IP parameter editors. Specifies the file prefix used for generating configuration files. Use a unique prefix for configuration files for each variant of the Native PHY and PLL. continued... ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 349 Clears the stored Native PHY/ATX PLL IP parameter settings for the profile specified by the Selected reconfiguration profile parameter. An empty profile defaults to the current parameter continued... ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 350 Parameter Editor, if one or more of the individual TX pin swing settings need to be changed, then enable the option to override the Intel- recommended defaults to individually modify the settings. For details about QSF assignments for the analog settings, refer to the Analog Parameter Settings chapter.
Page 351: Dynamic Reconfiguration Interface Merging Across Multiple Ip Blocks
The Native PHY provides the ability to create channels that are either simplex or duplex instances. However, each physical transceiver channel in Cyclone 10 GX devices is fully duplex. You can share the reconfiguration interfaces across different IP blocks by manually making a QSF assignment.
Page 352 Assign the two instances to be merged to the same reconfiguration group. You cannot merge multiple reconfiguration interfaces when ADME, optional reconfiguration logic, or embedded reconfiguration streamer are enabled in the Native (30) PHY IP core. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 353: Embedded Debug Features
For details on TTK usage refer to "Debugging Transceiver Links" in Intel Quartus Prime Pro Edition Handbook Volume 3: Verification. The Cyclone 10 GX Transceiver Native PHY, ATX PLL, fPLL, and CMU PLL IP cores provide the following optional debug features to facilitate embedded test and debug capability: •...
Page 354: Altera Debug Master Endpoint
6.15.2. Optional Reconfiguration Logic The Cyclone 10 GX Transceiver Native PHY, ATX PLL, fPLL, and CMU PLL IP cores contain soft logic for debug purposes known as the Optional Reconfiguration Logic. This soft logic provides a set of registers that enable you to determine the state of the Native PHY and PLL IP cores.
Page 355 Selects whether the receiver is listens to the AMDE override_set_rx_loc register or the set_rx_locktoref ktoref port. 1'b1 indicates that the rx_set_locktoref receiver listens to the ADME set_rx_locktoref register. continued... ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 356 Arbitration section for more details. For more details about calibration registers and performing user recalibration, refer to the Calibration chapter. The following control and status registers are available for the PLL IP cores. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 357 • PRBS Done bit—indicates the PRBS checker has had sufficient time to lock to the incoming pattern. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 358 0x302[7:0] Accumulated error count [15:8] Accumulated error count [15:8] 0x303[7:0] Accumulated error count [23:16] Accumulated error count [23:16] 0x304[7:0] Accumulated error count [31:24] Accumulated error count [31:24] continued... ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 359: Using Data Pattern Generators And Checkers
The pattern generators and checkers are supported only for non-bonded channels. 6.16.1. Using PRBS Data Pattern Generator and Checker Use the Cyclone 10 GX PRBS generator and checker to simulate traffic and easily characterize high-speed links without fully implementing any upper protocol stack layer.
Page 360 Polynomial 64-Bit 10-Bit PRBS7 G(x) = 1+ x PRBS9 G(x) = 1+ x PRBS15 G(x) = 1+ x PRBS23 G(x) = 1+ x PRBS31 G(x) = 1+ x ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 361 1'b1 Serializer 64-bit 0x110 [2:0] 3'b011 sixty_four_bit ser_mode width mode Serializer 10-bit 3'b100 ten_bit width mode (31) Enable xN non 0x111 [4:0] 5'b11000 xN_non_bonding x1_clock_source_sel bonding 0x119 1'b0 ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 362 To disable the PRBS generator and restore the design back to original bonded design, you need to restore the original value that was previously saved from registers 0x119[0], 0x111[4:0]. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 363 6. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic Reconfiguration. Note: A dash (-) indicates that the corresponding bit value should not be modified during read-modify-write. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 364 Reconfiguration. To disable the PRBS generator, write the original values back into the read-modify- write addresses in Register Map for PRBS Generators for bonded and non bonded designs. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 365 You must perform a sequence of read-modify-writes to the Transceiver Native PHY reconfiguration interface to enable the PRBS checker. You must perform read-modify- writes to addresses 0x00A, 0x00B, 0x00C, and 0x13F. To enable the PRBS checker, follow these steps: ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 366 2. Perform a read-modify-write to address x00A[7:0] with the following bits: 8’b1- - - - - - - 3. Perform a read-modify-write to address x00B[7:0] with the following bits: 8’b0000 11 - - ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 367 368 shows the addresses and bits to control the inversion of the PRBS generator or checker. To disable the PRBS pattern inversion for the PRBS generator or checker, follow these steps: ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 368: Using Pseudo Random Pattern Mode
328 6.16.2. Using Pseudo Random Pattern Mode You can use the Cyclone 10 GX Pseudo Random Pattern (PRP) generator and verifier in the scrambler and descrambler to generate random data pattern and seed that the scrambler can use. PRP mode is a test mode of the scrambler. Two seeds are available to seed the scrambler: all 0s or two local fault-ordered sets.
Page 369: Timing Closure Recommendations
328 6.17. Timing Closure Recommendations Intel recommends that you enable the multiple reconfiguration profiles feature in the Native PHY IP core if any of the modified or target configurations involve changes to PCS settings. Using multiple reconfiguration profiles is optional if the reconfiguration involves changes to only PMA settings such as PLL switching, CGB divider switching, and refclk switching.
Page 370 Based on how the clocks are connected in the design, you might have to include additional constraints to set false paths from the registers in the core logic to the clocks. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 371: Unsupported Features
-to [get_registers <Core Logic B>] 6.18. Unsupported Features The following features are not supported by either the Transceiver Native PHY IP core or the PLL IP reconfiguration interface: ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 372: Cyclone 10 Gx Transceiver Register Map
Use the register map in conjunction with a transceiver configuration file generated by the Cyclone 10 GX Native PHY IP core. This configuration file includes details about the registers that are set for a specific transceiver configuration. Do not use the register map to locate and modify specific registers in the transceiver.
Page 373: Calibration
Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 374 To check whether or not calibration is done, you can read the capability registers or check the signals. The from the *_cal_busy reconfig_waitrequest Avalon-MM reconfiguration interface is not a reliable indicator to check whether or not ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 375: Calibration Registers
Avalon Interface Specifications • Reconfiguration Interface and Dynamic Reconfiguration Chapter on page 315 7.2. Calibration Registers The Cyclone 10 GX transceiver PMA and PLLs include the following types of registers for calibration: • Avalon-MM interface arbitration registers • Calibration enable registers •...
Page 376: Transceiver Channel Calibration Registers
Fractional PLL Calibration Registers fPLL Calibration Enable Register Offset Address 0x100 Reserved fPLL calibration enable. Set 1 to enable calibration. (33) CDR/CMU PLL calibration is part of PMA RX calibration. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 377: Atx Pll Calibration Registers
To merge a Simplex TX and a Simplex RX channel into one physical channel, refer to Dynamic Reconfiguration Interface Merging Across Multiple IP Blocks on page 351. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 378 AVMM arbitration with PreSICE is enabled or not. 0x1: PreSICE is controlling the internal configuration bus. continued... ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 379: Rate Switch Flag Register
Avalon-MM reconfiguration register space. During RX PMA calibration (including CDR), PreSICE needs to know which set of CDR charge pump setting to use. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 380: Power-Up Calibration
Intel recommends that you wait until all signals are low before *_cal_busy requesting any access. All power-up calibration starts from voltage regulator (Vreg) calibration for all banks and channels.
Page 381 1. Vreg calibration for all banks and channels. 2. PCIe Hard IP 0 calibration (if used). 3. Calibration of all non-PCIe Hard IP channels in calibration sequence. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 382 RX PMA and TX PMA Calibration (1), (2) Notes: (1) CDR/CMU PLL calibration is part of RX PMA calibration. (2) For power-up calibration, RX PMA calibration happens before TX PMA calibration. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 383: User Recalibration
If you are recalibrating your fPLL, follow the fPLL-to-ATX PLL spacing guideline as stated in the "Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs" section under PLLs and Clock Networks chapter. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 384: User Recalibration Sequence
PLL reconfiguration, and PLL and channel interface switching, then you must reset the transceivers. The proper reset sequence is required after calibration. Intel recommends you use the Transceiver PHY Reset Controller IP which has...
Page 385: Calibration Example
PLL spacing guideline as stated in the "Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs" section under PLLs and Clock Networks chapter. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 386: Cdr/Cmu Pll Recalibration
6. Release the internal configuration bus to PreSICE to perform recalibration by writing 0x1 to offset address 0x0[7:0]. 7. Periodically check the output signals or read the capability registers *cal_busy 0x281[1:0] to check status until calibration is complete. *cal_busy ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 387: Calibration Revision History
For the Transceiver Channel PMA Calibration Registers table: Changed bit[6] from Reserved to Adaptation mode. Set 0, to disable adaptation mode. • Clarified the User Recalibration section. • Clarified the PMA Recalibration section. 2017.05.08 Initial release. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 388: Analog Parameter Settings
Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 389: Analog Parameter Settings List
Pre-emphasis D_POST_TAP Post-Tap Polarity XCVR_C10_TX_PRE_EMP_SWITCHI Transmitter Pre-Emphasis First Pre- TX serial data Pre-emphasis NG_CTRL_PRE_TAP_1T Tap Magnitude XCVR_C10_TX_PRE_EMP_SWITCHI Transmitter Pre-Emphasis Second TX serial data Pre-emphasis NG_CTRL_PRE_TAP_2T Pre-Tap Magnitude continued... ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 390: Receiver General Analog Settings
R_EXT0 Tristate R_R1 100 Ohm R_R2 85 Ohm Assign To RX serial data pin. Syntax set_instance_assignment -name XCVR_C10_RX_TERM_SEL <value> -to <rx_serial_data pin name> 8.5. Receiver Analog Equalization Settings ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 391: Ctle Settings
Equalizer DC gain setting 6 DC Gain 2 STG2_GAIN7 Equalizer DC gain setting 13 DC Gain 3 STG3_GAIN7 Equalizer DC gain setting 20 DC Gain 4 STG4_GAIN7 Equalizer DC gain setting 27 ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 392 CTLE is enabled. If configured in four stage mode, it has no effect on CTLE gain value. Table 220. Available Options Value Description RADP_CTLE_EQZ_1S_SEL_<0 to 15> CTLE AC Gain Setting < 0 to 15> ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 393: Vga Settings
VGA Output Voltage Swing Setting <0 to 4> Assign To RX serial data pin. Syntax set_instance_assignment -name XCVR_C10_RX_ADP_VGA_SEL <value> -to <rx_serial_data pin name> 8.6. Transmitter General Analog Settings ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 394: Xcvr_C10_Tx_Term_Sel
Value of XCVR_C10_TX_COMPENSATION_EN PCIe Gen1, Gen2 DISABLE Others ENABLE/DISABLE Assign To TX serial data pin. Syntax set_instance_assignment -name XCVR_C10_TX_COMPENSATION_EN <value> -to <tx_serial_data pin name> Related Information EPE (Early Power Estimator) ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 395: Xcvr_C10_Tx_Slew_Rate_Ctrl
8.7. Transmitter Pre-Emphasis Analog Settings The programmable pre-emphasis block in the transmit buffer amplifies the high frequencies in the transmit data to compensate for attenuation in the transmission media. ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 396: Xcvr_C10_Tx_Pre_Emp_Sign_Pre_Tap_1T
Table 228. Available Options Value Description FIR_PRE_2T_POS Positive pre-tap 2 FIR_PRE_2T_NEG Negative pre-tap 2 Assign To TX serial data pin. Syntax set_instance_assignment -name XCVR_C10_TX_PRE_EMP_SIGN_PRE_TAP_2T <value> -to <tx_serial_data pin name> ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 397: Xcvr_C10_Tx_Pre_Emp_Sign_1St_Post_Tap
Table 230. Available Options Value Description FIR_POST_2T_POS Positive post-tap 2 FIR_POST_2T_NEG Negative post-tap 2 Assign To TX serial data pin. Syntax set_instance_assignment -name XCVR_C10_TX_PRE_EMP_SIGN_2ND_POST_TAP <value> -to <tx_serial_data pin name> ® ® Intel Cyclone 10 GX Transceiver PHY User Guide Send Feedback...
Page 398: Xcvr_C10_Tx_Pre_Emp_Switching_Ctrl_Pre_Tap_1T
Available Options Value Description 0 – 16 Magnitude 0 – 16 Note: Refer to Cyclone 10 GX Pre-Emphasis and Output Swing Settings spreadsheet for selecting legal pre-emphasis and differential output voltage settings. Assign To TX serial data pin. Syntax set_instance_assignment -name XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T <value>...
Page 399: Xcvr_C10_Tx_Pre_Emp_Switching_Ctrl_1St_Post_Tap
Available Options Value Description 0 –25 Magnitude 0 –25 Note: Refer to Cyclone 10 GX Pre-Emphasis and Output Swing Settings spreadsheet for selecting legal pre-emphasis and differential output voltage settings. Assign To TX serial data pin. Syntax set_instance_assignment -name XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP <value> -to <tx_serial_data pin name>...
Page 400: Transmitter Vod Settings
Available Options Value Description 0 – 12 Magnitude 0 – 12 Note: Refer to Cyclone 10 GX Pre-Emphasis and Output Swing Settings spreadsheet for selecting legal pre-emphasis and differential output voltage settings. Assign To TX serial data. Syntax set_instance_assignment -name XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP <value>...
Page 401: Dedicated Reference Clock Settings
UG-20070 | 2018.09.24 Syntax set_instance_assignment -name XCVR_C10_TX_VOD_OUTPUT_SWING_CTRL <value> -to <tx_serial_data pin name> Related Information Cyclone 10 GX Pre-Emphasis and Output Swing Settings 8.9. Dedicated Reference Clock Settings 8.9.1. XCVR_C10_REFCLK_TERM_TRISTATE Pin planner or Assignment Editor Name Dedicated Reference Clock Pin Termination Description Specifies if the termination for dedicated reference clock pin is tri-stated.
Page 402: Unused Transceiver Channels Settings
8.10. Unused Transceiver Channels Settings Add the following Intel Cyclone 10 GX QSF assignments for RX pins to prevent performance degradation of unused receiver serial clocks over time. You can either use a global assignment or per-pin assignments. For per-pin assignments, you can specify a true or a complement RX pin.

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