Transceiver Phy Implementation - Intel Cyclone 10 GX User Manual

4.2. Transceiver PHY Implementation

Figure 146. Typical Transceiver PHY Implementation
clock
user reset
clk_usrpin
Notes:
(1) You can logical OR the pll_cal_busy and tx_cal_busy signals.
(2) tx_analogreset_ack and rx_analogreset_ack are status signals from the Transceiver PHY IP core when these ports are enabled for manual user implementation of Model 2.
Transceiver Reset Endpoints—The Transceiver PHY IP core contains Transceiver
Reset Endpoints (TREs)
Transceiver Reset Sequencer—The Quartus Prime software detects the presence of
TREs and automatically inserts only one Transceiver Reset Sequencer (TRS)
tx_analogreset
coded or Transceiver PHY Reset Controller) is received by the TREs. The TRE sends the
reset request to the TRS for scheduling. TRS schedules all the requested PMA resets
and sends them back to TREs. You can use either Transceiver PHY Reset Controller or
your own reset controller. However, for the TRS to work correctly, the required timing
duration must be followed. See
Note: The TRS IP is an inferred block and is not visible in the RTL. You have no control over
this block.
CLKUSR connection—The clock to the TRS must be stable and free-running
(100-125 MHz). By default, the Quartus Prime software automatically connects the
TRS clock input to the CLKUSR pin on the device. If you are using the CLKUSR pin for
your own logic (feeding it to the core), you must instantiate
altera_a10_xcvr_clock_module
altera_a10_xcvr_clock_module reset_clock (.clk_in(mgmt_clk));
For more information about the CLKUSR pin, refer to the Cyclone 10 GX Pin
Connection Guidelines.
(29)
There is only one centralized TRS instantiated for one or more Native PHY.
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
244
tx_analogreset
tx_digitalreset
Reset Controller
rx_analogreset
rx_digitalreset
(user-coded
or Intel IP)
tx_cal_busy (1)
rx_cal_busy
rx_is_lockedtoref
rx_is_lockedtodata
tx_analogreset_ack (2)
rx_analogreset_ack (2)
Transmit
PLL
Transceiver Reset Sequencer Inferred Block
(29)
.
and
rx_analogreset
Figure 147
4. Resetting Transceiver Channels
Transceiver PHY Instance
Transmitter
Transmitter
PCS
PMA
Receiver
Receiver
PCS
PMA
requests from the reset controller (User
on page 246 for required timing duration.
UG-20070 | 2018.09.24
Optional
(29)
. The
Send Feedback