Intel Cyclone 10 GX User Manual page 178

The following figure shows the current running disparity being altered in Basic single-
width mode by forcing a positive disparity /K28.5/ when it was supposed to be a
negative disparity /K28.5/. In this example, a series of /K28.5/ code groups are
continuously being sent. The stream alternates between a positive running disparity
(RD+) /K28.5/ and a negative running disparity (RD-) /K28.5/ to maintain a neutral
overall disparity. The current running disparity at time n + 3 indicates that the /K28.5/
in time n + 4 should be encoded with a negative disparity. Because
high at time n + 4, and
positive disparity code group.
Figure 105. 8B/10B TX Disparity Control
2.9.2.11. How to Enable Low Latency in Basic
In the Cyclone 10 GX Transceiver Native PHY IP Parameter Editor, use the following
settings to enable low latency:
1. Select the Enable 'Standard PCS' low latency mode option.
2. Select either low_latency or register FIFO in the TX FIFO mode list.
3. Select either low_latency or register FIFO in the RX FIFO mode list.
4. Select either Disabled or Serialize x2 in the TX byte serializer mode list.
5. Select either Disabled or Serialize x2 in the RX byte deserializer mode list.
6. Ensure that RX rate match FIFO mode is disabled.
7. Set the RX word aligner mode to bitslip.
8. Set the RX word aligner pattern length to 7 or 16.
Note: TX bitslip, RX bitslip, bit reversal, and polarity inversion modes are
2.9.2.12. TX Bit Slip
To use the TX bit slip, select the Enable TX bitslip and Enable
tx_std_bitslipboundarysel port options. This adds the
tx_std_bitslipboundarysel
number of bits specified by
bit slip. If there is more than one channel in the design,
tx_std_bitslipboundarysel
can verify this feature by monitoring the
Enabling the TX bit slip feature is optional.
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
178
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
tx_dispval
n
clock
tx_in[7:0]
BC
tx_ctrlenable
tx_forcedisp
tx_dispval
Current Running Disparity RD–
dataout[9:0]
17C
supported.
tx_std_bitslipboundarysel
is low, the /K28.5/ at time n + 4 is encoded as a
n + 1 n + 2 n + 3 n + 4
BC BC BC BC
RD+ RD– RD+ RD+
283 17C 283 283
input port. The TX PCS automatically slips the
ports are multiplied by the number of channels. You
tx_parallel_data
UG-20070 | 2018.09.24
tx_forcedisp
n + 5 n + 6 n + 7
BC BC BC
RD– RD+ RD–
17C 283 17C
. There is no port for TX
port.
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