Intel Cyclone 10 GX User Manual page 106

Table 95. Block Sync Parameters
Enable RX block synchronizer
Enable rx_enh_blk_lock port
Table 96. Gearbox Parameters
Enable TX data polarity inversion
Enable RX data polarity inversion
Table 97. Dynamic Reconfiguration Parameters
Enable dynamic reconfiguration
Share reconfiguration interface
Enable Altera Debug Master Endpoint
De-couple reconfig_waitrequest from calibration
Table 98. Configuration Files Parameters
Configuration file prefix
Generate SystemVerilog package file
Generate C header file
Generate MIF (Memory Initialization File)
Table 99. Generation Options Parameters
Generate parameter documentation file
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Intel Cyclone 10 GX Transceiver PHY User Guide
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UG-20070 | 2018.09.24
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