Intel Cyclone 10 GX User Manual page 207

3. PLLs and Clock Networks
UG-20070 | 2018.09.24
N Counter
The N counter divides the refclk mux's output. The N counter division helps lower the
loop bandwidth or reduce the frequency to within the phase frequency detector's
(PFD) operating range. Possible divide ratios are 1 (bypass), 2, 4, and 8.
Phase Frequency Detector (PFD)
The reference clock
feedback clock (
input to the PFD. The PFD output is proportional to the phase difference between the
two inputs. It aligns the input reference clock (
( ). The PFD generates an "Up" signal when the reference clock's falling edge
fbclk
occurs before the feedback clock's falling edge. Conversely, the PFD generates a
"Down" signal when feedback clock's falling edge occurs before the reference clock's
falling edge.
Charge Pump and Loop Filter (CP + LF)
The PFD output is used by the charge pump and loop filter to generate a control
voltage for the VCO. The charge pump translates the "Up"/"Down" pulses from the
PFD into current pulses. The current pulses are filtered through a low pass filter into a
control voltage which drives the VCO frequency.
Voltage Controlled Oscillator (VCO)
The CMU PLL has a ring oscillator based VCO. For VCO frequency range, refer to the
datasheet.
L Counter
The L counter divides the differential clocks generated by the CMU PLL.
M Counter
The M counter is used in the PFD's feedback path. The output of the L counter is
connected to the M counter. The combined division ratios of the L counter and the M
counter determine the overall division factor in the PFD's feedback path.
Lock Detector (LD)
The lock detector indicates when the CMU PLL is locked to the desired output's phase
and frequency. The lock detector XORs the "Up"/"Down" pulses and indicates when the
M counter's output and N counter's output are phase-aligned.
The reference clock (
detector block. There is a pre-divider to lower the frequency in case the frequency is
too high.
Related Information
• Calibration
• Cyclone 10 GX Device Datasheet
Send Feedback
signal at the output of the N counter block and the
(refclk)
) signal at the output of the M counter block is supplied as an
fbclk
) and feedback clock (
refclk
on page 373
) to the feedback clock
refclk
) are sent to the PCS's ppm
fbclk
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
207