Intel Cyclone 10 GX User Manual page 138

Master Clock Generation Block
MCGB
Include master clock generation block
Clock division factor
Enable x6/xN non-bnded high speed clock output port
Enable PCIe clock switch interface
Number of auxiliary MCGB clock input ports
MCGB input clock frequency
MCGB output data rate
Bonding
Enable bonding clock output ports
Enable feedback compensation bonding
PMA interface width
Dynamic Reconfiguration
Enable dynamic reconfiguration
Enable Altera Debug Master Endpoint
Separate avmm_busy from reconfig_waitrequest
Optional Reconfiguration Logic
Enable capability registers
Set user-defined IP identifier
Enable control and status registers
Configuration Files
Configuration file prefix
Generate SystemVerilog package file
Generate C Header file
Generate MIF (Memory Initialize file)
Generation Options
Generate parameter documentation file
Related Information
Using the Cyclone 10 GX Transceiver Native PHY IP Core
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
138
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
Parameter Gen1 PIPE
Disable for x1
Enable for x2, x4
N/A for x1
1 for x2, x4
N/A for x1
Disable for x2, x4
N/A for x1
Disable for x2, x4
N/A for x1
0 for x2, x4
1250 MHz
2500 Mbps
N/A for x1
Enable for x2, x4
N/A for x1 design
Disable for x2, x4
N/A for x1 design
10 for x2, x4
Disable
Disable
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Enable
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Gen2 PIPE
Disable for x1
Enable for x2, x4
N/A for x1
1 for x2, x4
N/A for x1
Disable for x2, x4
N/A for x1
Enable for x2, x4
N/A for x1
0 for x2, x4
2500 MHz
5000 Mbps
N/A for x1
Enable for x2, x4
N/A for x1 design
Disable for x2, x4
N/A for x1 design
10 for x2, x4
Disable
Disable
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Enable
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