Intel Cyclone 10 GX User Manual page 197

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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• Added a note "Link training, auto speed negotiation and sequencer functions are not included in the
Native PHY IP. The user would have to create soft logic to implement these functions when using
Native PHY IP" in the "Transceiver Protocols and PHY IP Support" section.
• Added a row for "CPRI 4.1/OBSAI RP3 v4.1" protocol in the "Transceiver Protocols and PHY IP
Support" section.
• Added footnote "For x2 and x4 modes, select PCIe PIPE Gen2 x8. Then change the number of data
channels from 8 to 4. " for "PCIe Gen2 x1, x2, x4" protocol in the "Transceiver Protocols and PHY IP
Support" section.
• Added footnotes in the "Transceiver Protocols and PHY IP Support" section.
• Updated protocol presets for "SD-SDI/HD-SDI/3G/6G/12G-SDI ", "DisplayPort" and "CPRI 4.1/
OBSAI RP3 v4.1" protocols in the "Transceiver Protocols and PHY IP Support" section.
• Added a note that Intel Cyclone 10 GX is only supported with Intel Quartus Prime Pro Edition 17.1
and future versions in the "Transceiver Design IP Blocks" section.
• Added a note "Intel Cyclone 10 GX only supported with Intel Quartus Prime Pro Edition 17.1 and
future versions."
• Added a note "Link training, auto speed negotiation and sequencer functions are not included in the
Native PHY IP. The user would have to create soft logic to implement these functions when using
Native PHY IP. " in the "Protocols and PHY IP Support" table.
• Added CPRI 4.1/OBSAI RP3 v4.1 protocol in "Protocols and PHY IP Support" table.
Made the following changes in the "10GBASE-R" section:
• Added the "Native PHY IP Parameter Settings for 10GBASE-R and 10GBASE-R with IEEE 1588v2"
section.
• Changed the range of values for the Number of data channels parameter in the "General and
Datapath Parameters" table.
• Changed the range of values for the Initial TX PLL clock input selection parameter in the "TX
PMA Parameters" table.
Made the following changes to the "XAUI PHY IP Core" section:
• Removed this section.
Made the following changes to the "Gigabit Ethernet (GbE) and GbE with 1588" section:
• Changed the note in the "Rate Match FIFO for GbE" section.
• Added the "Native PHY IP Parameter Settings for GbE and GbE with IEEE 1588v2" section.
Made the following changes to the "Using the Intel Cyclone 10 GX Transceiver Native PHY IP Core"
section:
• Added this chapter.
2017.05.08 Initial release.
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Intel Cyclone 10 GX Transceiver PHY User Guide
197