Transceiver Design Flow; Select And Instantiate The Phy Ip Core - Intel Cyclone 10 GX User Manual

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24

2.2. Transceiver Design Flow

Figure 8. Transceiver Design Flow
Generate the Transceiver PHY Reset Controller
or create your own User-Coded Reset Controller

2.2.1. Select and Instantiate the PHY IP Core

Select the appropriate PHY IP core to implement your protocol.
Refer to the Cyclone 10 GX Transceiver Protocols and PHY IP Support section to decide
which PHY IP to select to implement your protocol.
You can create your Quartus Prime project first, and then instantiate the various IPs
required for your design. In this case, specify the location to save your IP HDL files.
The current version of the PHY IP does not have the option to set the speed grade.
Specify the device family and speed grade when you create the Quartus Prime project.
You can also instantiate the PHY IP directly to evaluate the various features.
Send Feedback
Select PHY IP Core
Configure the PHY IP Core
Generate PHY IP Core
Connect PHY IP Core to PLL IP Core, Reset Controller, and
connect reconfiguration logic via Avalon-MM interface
Connect Transceiver Datapath to MAC IP Core or to a Data Generator / Analyzer
Make analog parameter settings to I/O pins using the Assignment Editor or updating the Quartus Prime Settings File
Select PLL IP Core
Configure the PLL IP Core
Generate PLL IP Core
Compile Design
Verify Design Functionality
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
Create reconfiguration logic
(if needed)
17