Transmitter Data Path Interface Clocking - Intel Cyclone 10 GX User Manual

3. PLLs and Clock Networks
UG-20070 | 2018.09.24
The output frequency of
of the following:
•
A divided down version of the
divide by 1 and divide by 2 ratios are available.
• A divided down version of the serializer clock where divide by 33, 40, and 66
ratios are available.
These clocks can be used to meet core timing by operating the TX and RX FIFO in
double-width mode, as this halves the required clock frequency at the PCS to/from
FPGA interface. These clocks can also be used to clock the core side of the TX and RX
FIFOs when the Enhanced PCS Gearbox is used.
For example, if you use the Enhanced PCS Gearbox with a 66:40 ratio, then you can
use
tx_pma_div_clkout
FIFO, instead of using a PLL to generate the required clock frequency, or using an
external clock source.

3.6. Transmitter Data Path Interface Clocking

The clocks generated by the PLLs are used to clock the channel PMA and PCS blocks.
The clocking architecture is different for the standard PCS and the enhanced PCS.
Figure 129. Transmitter Standard PCS and PMA Clocking
The master or the local CGB provides the high speed serial clock to the serializer of the transmitter PMA, and
the low speed parallel clock to the transmitter PCS.
Transmitter PMA
Parallel and Serial Clock
In the Standard PCS, for configurations that do not use the byte serializer, the parallel
clock is used by all the blocks up to the read side of the TX phase compensation FIFO.
For configurations that use the byte serializer block, the clock divided by 2 or 4 is used
by the byte serializer and the read side of the TX phase compensation FIFO. The clock
used to clock the read side of the TX phase compensation FIFO is also forwarded to
the FPGA fabric to provide an interface between the FPGA fabric and the transceiver.
If the
tx_clkout
of the phase compensation FIFO, then both sides of the FIFO have 0 ppm frequency
difference because it is the same clock that is used.
Send Feedback
tx_pma_div_clkout
with a divide-by-33 ratio to clock the write side of the TX
tx_clkout
tx_pma_div_clkout
From Receiver Standard PCS
Parallel Clock
Serial Clock
that is forwarded to the FPGA fabric is used to clock the write side
and
rx_pma_div_clkout
or
tx_clkout rx_clkout
PRBS
Generator
/2, /4
Clock Generation Block (CGB)
Clock Divider
Parallel and Serial Clock
®
Intel Cyclone
can be one
respectively, where
Transmitter Standard PCS FPGA
Fabric
tx_coreclkin
tx_clkout
ATX PLL
CMU PLL
fPLL
Serial Clock
Input Reference Clock
®
10 GX Transceiver PHY User Guide
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