Intel Cyclone 10 GX User Manual page 119

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Signal Name
RX XGMII signals—synchronous to
xgmii_rx_data
xgmii_rx_control
xgmii_rx_valid
Send Feedback
Direction Width
xgmii_rx_coreclkin
Output 32
Output 4
Output 1
Description
Speed
2.5G Asserted once every 4
clock cycles
5G Asserted once every 2
clock cycles
10G Asserted in every clock
cycle
RX data to the MAC. The PHY sends the data in the
following order: bits[7:0], bits[15:8], and so forth.
The width is:
• 32 bits for 10M/100M/1G/2.5G/5G/10G
(USXGMII) configurations.
RX control to the MAC.
•
[0] corresponds to
xgmii_rx_control
[7:0]
xgmii_rx_data
•
[1] corresponds to
xgmii_rx_control
[15:8]
xgmii_rx_data
• and so forth.
The width is:
• 4 bits for 10M/100M/1G/2.5G/5G/10G
(USXGMII) configurations.
Indicates valid data on
xgmii_rx_control
from the MAC.
xgmii_rx_data
The toggle rate from the PHY is shown in the table
below.
Note: The toggle rate may vary when the start of
a packet is received or when rate match
occurs inside the PHY. You should not
expect the valid data pattern to be fixed.
Speed
10M Asserted every 1000
clock cycles
100M Asserted every 100
clock cycles
1G Asserted once every 10
clock cycles
2.5G Asserted once every 4
clock cycles
5G Asserted once every 2
clock cycles
10G Asserted in every clock
cycle
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
Toggle Rate
and
Toggle Rate
119