Intel Cyclone 10 GX User Manual page 169

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Note: •
rx_patterndetect
•
rx_syncstatus
•
rx_std_wa_patternalign
•
If there is more than one channel in the design,
rx_syncstatus
bit corresponds to one channel.
You can verify this feature by monitoring
The following timing diagrams demonstrate how to use the ports and show the
relationship between the various control and status signals. In the top waveform,
rx_parallel_data
rx_std_wa_patternalign
the behavior of the
aligned.
Figure 85. Manual Mode when the PCS-PMA Interface Width is 8 Bits
tx_parallel_data
rx_std_wa_patternalign
tx_parallel_data
rx_parallel_data
rx_patterndetect
rx_syncstatus
rx_std_wa_patternalign
tx_parallel_data
rx_parallel_data
rx_patterndetect
rx_syncstatus
In manual alignment mode, the word alignment operation is manually controlled with
the
rx_std_wa_patternalign
The word aligner operation is level-sensitive to
aligner asserts the
aligns to the new word boundary.
Send Feedback
is asserted whenever there is a pattern match.
is asserted after the word aligner achieves synchronization.
is asserted to re-align and resynchronize.
and
rx_std_wa_patternalign
is initially misaligned. After asserting the
signal, it becomes aligned. The bottom waveform shows
signal when
rx_syncstatus
= 8'hBC and the word aligner pattern = 8'hBC
bc
00
bc
bc
input signal or the
signal for one parallel clock cycle whenever it re-
rx_syncstatus
rx_patterndetect
become buses in which each
.
rx_parallel_data
rx_parallel_data
bc
rx_enapatternalign
rx_enapatternalign
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
,
is already
register.
. The word
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