Intel Cyclone 10 GX User Manual page 204

When in core mode, for the fPLL to generate output clocks with a fixed frequency and
phase relation to an input reference clock, the Enable phase alignment option must
be selected. In the fractional frequency mode, the fPLL supports data rates from 1
Gbps to 12.5 Gbps.
Input Reference Clock
This is the dedicated input reference clock source for the PLL.
The input reference clock can be sourced from one of the following:
• Dedicated reference clock pin
• Reference clock network
• Receiver input pin
• Output of another fPLL with PLL cascading
• Global clock or the core clock network
The input reference clock is a differential signal. Intel recommends using the
dedicated reference clock pin as the input reference clock source for best jitter
performance. For protocol jitter compliance at datarate > 10 Gbps, Intel recommends
using the dedicated reference clock pin in the same triplet with the fPLL as the input
reference clock source. The input reference clock must be stable and free-running at
device power-up for proper PLL operation. If the reference clock is not available at
device power-up, then you must recalibrate the PLL when the reference clock is
available.
Note: The fPLL calibration is clocked by the CLKUSR clock, which must be stable and
available for the calibration to proceed. Refer to the
for details about PLL calibration and CLKUSR clock.
Reference Clock Multiplexer
The
refclk
reference clock sources.
N Counter
The N counter divides the reference clock (
division helps lower the loop bandwidth or reduce the frequency within the phase
frequency detector's (PFD) operating range. The N counter supports division factors
from 1 to 32.
Phase Frequency Detector
The reference clock
feedback clock
inputs to the PFD. The output of the PFD is proportional to the phase difference
between the
The PFD generates an "Up" signal when the reference clock's falling edge occurs
before the feedback clock's falling edge. Conversely, the PFD generates a "Down"
signal when the feedback clock's falling edge occurs before the reference clock's falling
edge.
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
204
mux selects the reference clock to the PLL from the various available
signal at the output of the N counter block and the
(refclk)
signal at the output of the M counter block are supplied as an
(fbclk)
and inputs. The PFD aligns the
refclk fbclk
3. PLLs and Clock Networks
Calibration on page 373 section
) mux's output. The N counter
refclk
fbclk
UG-20070 | 2018.09.24
to the .
refclk
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