Intel Cyclone 10 GX User Manual page 56

Name
tx_enh_fifo_full[<n>-1
:0]
tx_enh_fifo_pfull[<n>-
1:0]
tx_enh_fifo_empty[<n>-
1:0]
tx_enh_fifo_pempty[<n>
-1:0]
Table 46. Enhanced PCS RX FIFO
Name
rx_enh_data_valid[<n>
-1:0]
rx_enh_fifo_full[<n>-
1:0]
rx_enh_fifo_pfull[<n>
-1:0]
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
56
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
Direction Clock Domain
Output Synchronous to
the clock driving
the write side of
the FIFO
(
tx_coreclkin
or
tx_clkout
Output Synchronous to
the clock driving
the write side of
the FIFO
tx_coreclkin
or
tx_clkout
Output Synchronous to
the clock driving
the write side of
the FIFO
tx_coreclkin
or
tx_clkout
Output Synchronous to
the clock driving
the write side of
the FIFO
tx_coreclkin
or
tx_clkout
Direction Clock Domain
Output Synchronous to
the clock driving
the read side of
the FIFO
rx_coreclkin
or
rx_clkout
Output Synchronous to
the clock driving
the read side of
the FIFO
rx_coreclkin
or
rx_clkout
Output Synchronous to
the clock driving
the read side of
Description
Refer to Enhanced PCS FIFO Operation
more details.
Assertion of this signal indicates the TX FIFO is full.
Because the depth is always constant, you can ignore this
signal for the phase compensation mode.
Refer to Enhanced PCS FIFO Operation
more details.
)
This signal gets asserted when the TX FIFO reaches its
partially full threshold. Because the depth is always
constant, you can ignore this signal for the phase
compensation mode.
Refer to Enhanced PCS FIFO Operation
more details.
When asserted, indicates that the TX FIFO is empty. This
signal gets asserted for 2 to 3 clock cycles. Because the
depth is always constant, you can ignore this signal for
the phase compensation mode.
Refer to Enhanced PCS FIFO Operation
more details.
When asserted, indicates that the TX FIFO has reached its
specified partially empty threshold. When you turn this
option on, the Enhanced PCS enables the
port, which is asynchronous. This
tx_enh_fifo_pempty
signal gets asserted for 2 to 3 clock cycles. Because the
depth is always constant, you can ignore this signal for
the phase compensation mode.
Refer to Enhanced PCS FIFO Operation
more details.
Description
When asserted, indicates that
valid. Discard invalid RX parallel data
when
rx_enh_data_valid
This option is available when you select the following
parameters:
• Enhanced PCS Transceiver configuration rules
specifies Interlaken
• Enhanced PCS Transceiver configuration rules
specifies Basic, and RX FIFO mode is Phase
compensation
• Enhanced PCS Transceiver configuration rules
specifies Basic, and RX FIFO mode is Register
Refer to Enhanced PCS FIFO Operation
for more details.
When asserted, indicates that the RX FIFO is full. This
signal gets asserted for 2 to 3 clock cycles.Because
the depth is always constant, you can ignore this
signal for the phase compensation mode.
Refer to Enhanced PCS FIFO Operation
for more details.
When asserted, indicates that the RX FIFO has
reached its specified partially full threshold. This signal
gets asserted for 2 to 3 clock cycles. Because the
depth is always constant, you can ignore this signal
for the phase compensation mode.
UG-20070 | 2018.09.24
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is
rx_parallel_data
signal is low.
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continued...
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