Atx Pll Ip Parameter Core Settings For Pipe - Intel Cyclone 10 GX User Manual

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Parameter
Configuration Files
Configuration file prefix
Generate SystemVerilog package file
Generate C Header file
Generate MIF (Memory Initialize file)
Generation Options
Generate parameter documentation file
Related Information
Using the Cyclone 10 GX Transceiver Native PHY IP Core

2.7.7. ATX PLL IP Parameter Core Settings for PIPE

Table 125. Parameters for Cyclone 10 GX ATX PLL IP core in PIPE Gen1, Gen2 modes
This section contains the recommended parameter values for this protocol. Refer to Using the Cyclone 10 GX
Transceiver Native PHY IP Core for the full range of parameter values.
PLL
General
Message level for rule violations
Protocol Mode
Bandwidth
Number of PLL reference clocks
Selected reference clock source
Ports
Primary PLL clock output buffer
Enable PLL GX clock output port
Enable PCIe clock output port pll_pcie_clk
Enable ATX to fPLL cascade clock output port
Output Frequency
PLL output frequency
PLL output datarate
Enable fractional mode
PLL integer reference clock frequency
Configure counters manually
Multiple factor (M counter)
Divide factor (N counter)
Divide factor (L counter)
Send Feedback
N/A
N/A
N/A
N/A
Enable
Parameter
Gen1 PIPE
N/A
N/A
N/A
N/A
Enable
Gen1 PIPE
Error
PCIe Gen 1
Low, medium, high
1
0
GX clock output buffer
Enable
Enable
Disable
1250MHz
2500Mbps
Disable
100MHz, 125MHZ
Disable
N/A
N/A
N/A
®
Intel Cyclone
Gen2 PIPE
on page 26
Gen2 PIPE
Error
PCIe Gen 2
Low, medium, high
1
0
GX clock output buffer
Enable
Enable
Disable
2500MHz
5000Mbps
Disable
100MHz, 125MHZ
Disable
N/A
N/A
N/A
continued...
®
10 GX Transceiver PHY User Guide
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