Intel Cyclone 10 GX User Manual page 35

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Parameter
Enable Enhanced PCS
low latency mode
Enable RX/TX FIFO
double width mode
Table 13. Enhanced PCS TX FIFO Parameters
Parameter
TX FIFO Mode
TX FIFO partially full
threshold
TX FIFO partially
empty threshold
Enable tx_enh_fifo_full
port
Send Feedback
Range
The 67-bit FPGA fabric to PCS interface width uses the 64-bits from
the TX and RX parallel data. The block synchronizer determines the
block boundary of the 67-bit word with lower 3 bits from the control
bus.
On/Off Enables the low latency path for the Enhanced PCS. When you turn
on this option, the individual functional blocks within the Enhanced
PCS are bypassed to provide the lowest latency path from the PMA
through the Enhanced PCS.
On/Off Enables the double width mode for the RX and TX FIFOs. You can
use double width mode to run the FPGA fabric at half the frequency
of the PCS.
Range
Phase-Compensation Specifies one of the following modes:
Register •
Interlaken
Basic
Fast Register
•
•
•
•
10, 11, 12, 13 Specifies the partially full threshold for the Enhanced PCS TX FIFO.
Enter the value at which you want the TX FIFO to flag a partially
full status.
2, 3, 4, 5 Specifies the partially empty threshold for the Enhanced PCS TX
FIFO. Enter the value at which you want the TX FIFO to flag a
partially empty status.
On / Off Enables the tx_enh_fifo_full port. This signal indicates when the
TX FIFO is full. This signal is synchronous to
Description
Description
Phase Compensation: The TX FIFO compensates for the clock
phase difference between the read clock
write clocks or
tx_coreclkin
to 1'b1.
tx_enh_data_valid
Register: The TX FIFO is bypassed. The
and
tx_control tx_enh_data_valid
FIFO output. Assert
tx_enh_data_valid
times. The user must connect the write clock
the read clock .
tx_clkout
Interlaken: The TX FIFO acts as an elastic buffer. In this mode,
there are additional signals to control the data flow into the
FIFO. Therefore, the FIFO write clock frequency does not have
to be the same as the read clock frequency. You can control
writes to the FIFO with
tx_enh_data_valid
the FIFO flags, you can avoid the FIFO full and empty
conditions. The Interlaken frame generator controls reads.
Basic: The TX FIFO acts as an elastic buffer. This mode allows
driving write and read side of FIFO with different clock
frequencies. or
tx_coreclkin
minimum frequency of the lane data rate divided by 66. The
frequency range for
tx_coreclkin
rate/32) - (data rate/66). For best results, Intel recommends
that or
tx_coreclkin rx_coreclkin
Monitor FIFO flag to control write and read operations. For
additional details refer to Enhanced PCS FIFO Operation
164 section
Fast Register: The TX FIFO allows a higher maximum
frequency (f ) between the FPGA fabric and the TX PCS at the
MAX
expense of higher latency.
® ®
Intel Cyclone
and the
rx_clkout
. You can tie
tx_clkout
tx_parallel_data
are registered at the
port 1'b1 at all
tx_coreclkin
. By monitoring
must have a
rx_coreclkin
or is (data
rx_coreclkin
= (data rate/32).
on page
.
tx_coreclkin
continued...
10 GX Transceiver PHY User Guide
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