Cyclone 10 Gx Standard Pcs Architecture - Intel Cyclone 10 GX User Manual

5. Cyclone 10 GX Transceiver PHY Architecture
UG-20070 | 2018.09.24
Case
4
Figure 194. IDLE Word Insertion
This figure shows the insertion of IDLE words in the receiver data stream.
rx_parallel_data[79:0]
rx_parallel_data[79:0]
5.2.2.10.5. Basic Mode
In Basic mode, the RX FIFO operates as an elastic buffer, where buffer depths can
vary. This mode allows driving write and read side of RX FIFO with different clock
frequencies. Monitor the FIFO flag to control write and read operations. For RX FIFO,
assert
rx_enh_read_en

5.3. Cyclone 10 GX Standard PCS Architecture

The standard PCS can operate at a data rate of up to 10.8 Gbps. Protocols such as
PCI-Express, CPRI 4.1, GigE, IEEE 1588 are supported in Hard PCS while the other
protocols can be implemented using Basic/Custom (Standard PCS) transceiver
configuration rules.
Figure 195. Standard PCS Datapath Diagram
Send Feedback
Word
LW
UW
LW
Before Insertion
FD000000000004AEh
After Insertion
FD000000000004AEh
signal with
Transmitter PMA
tx_clkout
tx_pma_div_clkout
Receiver PMA
Parallel Clock
(Recovered) rx_clkout
tx_clkout
Parallel Clock
(From Clock
Divider)
Parallel Clock
Serial Clock
Parallel and Serial Clock
Input
I-DS I-DS
S I-In
OS
BBBBBB9CDDDDDD9Ch 00000000000000FBh
BBBBBB9CDDDDDD9Ch 0707070707070707h
signal going low.
rx_fifo_pfull
PRBS
Generator
/2, /4
/2, /4
PRBS
Verifier
rx_pma_div_clkout
Clock Generation Block (CGB)
Clock Divider
Parallel and Serial Clock
®
Intel Cyclone
Output
I-In
S
OS I-In
AAAAAAAAAAAAAAAAh
00000000000000FBh
Idle Inserted
Transmitter Standard PCS FPGA
Fabric
tx_coreclkin
tx_clkout
Receiver Standard PCS
rx_coreclkin
rx_clkout or
tx_clkout
ATX PLL
CMU PLL
fPLL
Serial Clock
®
10 GX Transceiver PHY User Guide
299