Intel Cyclone 10 GX User Manual page 263

4. Resetting Transceiver Channels
UG-20070 | 2018.09.24
Name
Enable RX channel reset control
Use separate RX reset per channel
RX digital reset mode
rx_analogreset duration
rx_digitalreset duration
Send Feedback
Range
RX Channel
On /Off
On /Off
Auto, Manual, Expose
Port
1-999999999
1-999999999
Description
value of 0 adds no hysteresis. A higher value filters
glitches on the signal. Intel
pll_locked
recommends that the amount of hysteresis be
longer than
tpll_lock_max_time
When On, each RX channel has a separate reset
input. When Off, each RX channel uses a shared
RX reset input for all channels. This implies that if
one of the RX channels is not locked, all the other
RX channels will be held in reset until all RX
channels are locked. Digital reset stays asserted
until all RX channels have acquired lock.
When On, each RX channel has a separate reset
input. When Off, uses a shared RX reset controller
for all channels.
Specifies the Transceiver PHY Reset Controller
behavior when the PLL lock signal is deasserted.
The following modes are available:
• Auto—The associated
rx_digitalreset
controller automatically resets whenever the
signal is deasserted.
rx_is_lockedtodata
•
Manual—The associated
rx_digitalreset
controller is not reset when the
signal is deasserted,
rx_is_lockedtodata
allowing you to choose corrective action.
•
Expose Port—The
rx_manual
level signal of the IP core. If the core includes
separate reset control for each RX channel,
each RX channel uses its respective
signal for automatic
rx_is_lockedtodata
reset control; otherwise, the inputs are ANDed
to provide internal status for the shared reset
controller.
Specifies the time in ns to continue to assert the
after the reset input and all
rx_analogreset
other gating conditions are removed. The value is
rounded up to the nearest clock cycle. The default
value is 40 ns.
Note: Model 1 requires this to be set to 70 µs.
Select the Cyclone 10 GX Default
Settings preset.
Specifies the time in ns to continue to assert the
after the reset input and all
rx_digitalreset
other gating conditions are removed. The value is
rounded up to the nearest clock cycle. The default
value is 4000 ns.
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
.
signal is a top-
263