Intel Cyclone 10 GX User Manual page 182

2.9.2.17. Native PHY IP Parameter Settings for Basic, Basic with Rate Match
Configurations
This section contains the recommended parameter values for this protocol. Refer to
Using the Cyclone 10 GX Transceiver Native PHY IP Core for the full range of
parameter values.
Table 147. General and Datapath Options Parameters
Message level for rule violations
Transceiver configuration rules
PMA configuration rules
Transceiver mode
Number of data channels
Data rate
Enable datapath and interface reconfiguration
Enable simplified data interface
Table 148. TX PMA Parameters
TX channel bonding mode
PCS TX channel bonding master
Actual PCS TX channel bonding master
TX local clock division factor
Number of TX PLL clock inputs per channel
Initial TX PLL clock input selection
Enable tx_pma_clkout port
Enable tx_pma_div_clkout port
tx_pma_div_clkout division factor
Enable tx_pma_elecidle port
Enable rx_seriallpbken port
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Intel Cyclone 10 GX Transceiver PHY User Guide
182
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
Parameter
Parameter
UG-20070 | 2018.09.24
Range
error
warning
Basic/Custom (Standard PCS)
Basic/Custom w/Rate Match (Standard
PCS)
basic
TX/RX Duplex
TX Simplex
RX Simplex
to
1 12
Mbps to
611 10.81344
On/Off
On/Off
Range
Not bonded
PMA-only bonding
PMA and PCS bonding
Auto, n-1 (where n = the number of data
channels)
n-1 (where n = the number of data channels)
1, 2, 4, 8
1, 2, 3, 4
0 (Depends on the Number of TX PLL clock
inputs per channel value)
On/Off
On/Off
Disabled, 1, 2, 33, 40, 66
On/Off
On/Off
Gbps
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